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1 of 44 rev: 101405 general description the ds33r11/ds33zh11 design kit is an easy-to- use evaluation board for the ds33r11 and the ds33zh11 ethernet transport-over-serial link devices. the ds33zh11 section of the design kit contains an option for either t3e3 or t1e1 serial links. the ds33r11 chipset has an integrated t1e1 transceiver. all serial links are complete with line interface, transformers, and network connections. dallas chipview software is provided with the design kit, giving point-and-click access to configuration and status registers from a windows ? -based pc. on-board leds indicate receive loss-of-signal, queue overflow, ethernet link, tx/rx, and interrupt status. windows is a registered trademark of microsoft corp. design kit contents DS33R11DK/ds33zh11dk main board (ds33r11 + ds33zh11) cd rom: chipview software and manual DS33R11DK/ds33zh11dk data sheet configuration files features demonstrates key functions of ds33r11 and ds33zh11 ethernet transport chipsets ds33zh11 section includes ds21348 t1e1 liu and ds3150 t3e3 liu, transformers, bnc and rj48 network connectors and termination provides support for hardware and software modes on-board mmc2107 processor and chipview software provide point-and-click access to ds33r11 register set all ds33r11 and ds33zh11 interface pins are easily accessible for external data source/sink leds for loss-of-signal, queue overflow, ethernet link, tx/rx, and interrupt status easy-to-read silkscreen labels identify the signals associated with all connectors, jumpers, and leds ordering information part description DS33R11DK design kit for ds33r11 and ds33zh11 www.maxim-ic.com DS33R11DK/ds33zh11dk ethernet transport design kit downloaded from: http:///
DS33R11DK/ds33zh11dk 2 of 44 table of contents general desc ription ..........................................................................................................1 design kit conten ts............................................................................................................ 1 ordering in format ion .......................................................................................................1 componen t list ................................................................................................................. ....3 system fl oorplan ............................................................................................................... 8 pc board errata ................................................................................................................ ..8 file lo cations ................................................................................................................. ......9 basic op eration................................................................................................................ ..10 p owering u p the d esign k it ............................................................................................................... 10 general ........................................................................................................................ ....................................... 10 b asic ds33r11 i nitialization .............................................................................................................. 10 additional configur ation for ds33r11 ........................................................................................... .................... 10 b asic ds33zh11 i nitialization ............................................................................................................ 11 additional configurat ion for ds 33zh11 .......................................................................................... ................... 11 m onitor and c apture e thernet t raffic ............................................................................... 11 leds, configuration switches, jumpers, and connectors ..............................12 address map (a ll cards) ................................................................................................16 ds33r11 info rmation .........................................................................................................16 DS33R11DK/ds33zh11 dk informat ion ............................................................................17 technical su pport ............................................................................................................17 schema tics ..................................................................................................................... ......17 downloaded from: http:///
DS33R11DK/ds33zh11dk 3 of 44 component list designation qty description supplier/part number c01, c28, cb03, cb49, cb136, cb146, cb192, cp01, cp2, cp03 10 470 f 20%, 6.3v tantalum capacitors (d case) kem t491d477m006as c02, c11, c30, cb36, cb37, cb40Ccb43, cb45, cb153, cb195, cb197 13 1 f 10%, 16v ceramic capacitors (1206) panasonic ecj-3yb1c105k c03Cc06, c13, c14, c17, c20, c22, c26, c29, . . .incomplete listing (94 devices total) 94 0.1 f 10%, 16v ceramic capacitors (0603) phycomp 06032r104k7b20d c07, c08, c09, c12, c16, c18, c19, c21, c23, c24, c31, . . . incomplete listing (81 devices total) 81 10 f 20%, 10v ceramic capacitors (1206) panasonic ecj-3yb1a106m c10, cb23, cb24, cb26, cb33, cb91, cb95, cb151, cb161, cb162, cb175, cb177, cb181, cb185, cb189, cb190 16 0.1 f 20%, 16v x7r ceramic capacitors (0603) avx 0603yc104mat c15, cb76, cb77, cb169, cb179, cb188 6 10 f 20%, 10v ceramic capacitors (1206) panasonic ecj-3yb1a106m c25, c27, cb154C cb156, cb158Ccb160, cb166, cb173, cb174, cb182, cb183 13 4.7 f, 6.3v ceramic multilayer capacitors (0603) unk ecj-1vb0j475m cb105 1 0.1 f 10%, 16v ceramic capacitor (0805) phycomp 08052r104k7b20d cb180 1 1 f 10%, 16v ceramic capacitor (1206) panasonic ecj-3yb1c105k db01 1 1a, 40v schottky diode international rectifier 10bq040 ds01, ds02, ds05, ds13, ds14 5 red leds (smd) panasonic ln1251c ds03, ds08, ds15, ds19 4 red leds (smd) panasonic ln1251c ds04, ds07, ds12, ds21 4 green leds (smd) panasonic ln1351c ds06, ds09, ds10, ds11, ds16, d17, ds18, ds20 8 amber leds (smd) panasonic ln1451c gnd_tp01, gnd_tp02, gnd_tp03, gnd_tpb01, gnd_tpp01C gnd_tpp23 27 standard ground clip keystone 4954 h01Ch06, hb01, hb02, hb03 9 kit, 4-40 hardware, 0.5" nylon standoff and nylon hex-nut lab stock 4-40kit6 downloaded from: http:///
DS33R11DK/ds33zh11dk 4 of 44 designation qty description supplier/part number j01, j05, j06, j18, j36 5 terminal strip (10-pin, dual row, vertical) samtec tsw-105-07-t-d j02 1 db9 right-angle connector (long case) amp 747459-1 j03, j10, j11, j14Cj17, j25, j26, j27, j32, j34, j35 13 100-mil, 2-position jumpers lab stock not applicable j04 1 100-mil, 2 x 7-position jumper lab stock not applicable j07, j08, j09 3 not populated 14-pin headers, dual row, vertical samtec nopop-hdr-tsw-107-14-t-d j12, j13, j22, j23, j30, j33 6 l_terminal strip, 10 pin, dual row, vert do not popluate dnp j19, j24 2 not populated 5-pin connectors, bnc 75 ? , right angle trompetor nopop-ucbjr220 j20, jb03 2 8-pin single-port rj48 connectors molex 15-43-8588 j21, j37 2 8-pin connectors (fastjack single, for national phy) halo electronics hfj11-2450e j28, j29, j31 3 20-pin headers (dual row, vertical) samtec hdr-tsw-110-14-t-d j38, j39 2 5-pin bnc connectors (75 ? , right angle) trompetor ucbjr220 j40, j41 2 5-pin bnc connectors (right angle) trompetor ucbjr220 jb01, jb05 2 sockets, banana plug, horizontal, black mouser electronics 164-6218 jb02, jb04 2 sockets, banana plug, horizontal, red mouser electronics 164-6219 jp01Cjp11, jpb01 12 100-mil, 3-position jumpers lab stock not applicable r1, r2 2 1.0k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj103v r01 1 1.0m ? 5%, 1/16w resistor (0603) panasonic erj-3geyj105v r02 1 10k ? 1%, 1/10w resistor (0805) panasonic erj-6enf1002v r03, r04, r05, r09, r14, r15, r21, rb35, rb52, rb53, rb58, rb69, rb70, rb73, rb77Crb86, rb89, rb90, rb93Crb96, rb101, rb132, rb133, rb137, rb138, rb144, rb151Crb155, rb159, rb162 43 30 ? , 1/16w resistors (0603) panasonic erj-3geyj300v r06, r08, r23, r24 4 49.9 ? 1%, 1/16w resistors (0603) panasonic erj-3ekf49r9v downloaded from: http:///
DS33R11DK/ds33zh11dk 5 of 44 designation qty description supplier/part number r07, r10, r12, r13, rb15 5 0 ? 5%, 1/16w resistors (0603) panasonic erj-3gey0r00v r11, rb167 2 10.0k ? 1%, 1/16w resistors (0603 ) panasonic erj-3ekf1002v r16Cr19 4 0 ? 5%, 1/10w resistors (0805) panasonic erj-6gey0r00v r20, r22 2 330 ? 5%, 1/8w resistors (1206) panasonic erj-8enf3300v rb01Crb03, rb06C rb13, rb17, rb18, rb22, rb25, rb27, rb28, rb32, rb33 19 10k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj103v rb04, rb05, rb30, rb31, rb34, rb36C rb43, rb59Crb61, rb63, rb99, rb100, rb150 20 10k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj103v rb129 1 30 ? 5%, 1/16w resistor (0603) panasonic erj-3geyj300v rb14, rb19, rb44C rb47, rb49Crb51, rb54, rb97, rb98, rb102, rb104, rb116, rb178 16 2.0k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj202v rb148, rb149 2 61.9 ? 1%, 1/10w resistors (0805) panasonic erj-6enf61r9v rb156 1 330 ? 5%, 1/10w resistor (0805) panasonic erj-6geyj331v rb16, rb20, rb48, rb66, rb67, rb68, rb71, rb74, rb75, rb135, rb142, rb146, rb157, rb161, rb165, rb169, rb174, rb176 18 330 ? 5%, 1/16w resistors (0603) panasonic erj-3geyj331v rb177 1 51.1 ? 1%, 1/10w resistor (0805) panasonic erj-6enf51r1v rb21, rb23 2 330 ? 5%, 1/16w resistors (0603) panasonic erj-3geyj331v rb24 1 1.0k ? 5%, 1/16w resistor (0603) panasonic erj-3geyj102v rb26, rb103, rb105C rb115, rb117Crb128, rb130, rb131, rb134, rb136, rb139Crb141, rb143, rb163, rb166, rb170 36 1.0k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj102v rb29 1 0 ? 5%, 1/8w resistor (1206) panasonic erj-8geyj0r00v downloaded from: http:///
DS33R11DK/ds33zh11dk 6 of 44 designation qty description supplier/part number rb55, rb56, rb57, rb62, rb64, rb65, rb72, rb76, rb145, rb147, rb158, rb160, rb164, rb168, rb173, rb175 16 5.1k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj512v rb87, rb91 2 60.4 ? 1%, 1/10w resistors (0805) panasonic erj-6enf60r4v rb88, rb92, rb171, rb172 4 54.9 ? 1%, 1/16w resistors (0603) panasonic erj-3ekf54r9v short01 1 2-position smd jumper do not populate. intended to have solder bridge during assembly. not populated sw01, sw02 2 4-pin single-pole switch panasonic evqpae04m t01 1 16-pin dual smt transformer pulse engineering tx1099 t02, t03 2 6-pin smt transformers (1:2ct, transmitter/receiver) pulse engineering pe-65968 tb01 1 12-pin smt transformer (1ct:1ct and 1ct:2ct) pulse engineering pe-68877 tp01Ctp03, tpb01C tpb11, tpp01,tpp02 16 test points (one plated hole) do not stuff. u01, u15 2 microprocessor voltage monitors 2.93v reset, 4-pin sot143 maxim max811seus-t u02 1 2mb spi serial eeprom 8-pin so, 2.7v to 3.6v atmel at25f2048n-10su-2.7 u03 1 mmc2107 processor motorola mmc2107 u04 1 fpga ic 1.2v, 20mm x 20mm, 144-pin tqfp lattice semiconductor lfec3e-3t144c u05, ub03 2 cypress sram, lab stock lab stock u06, u07 2 high-speed inverters fairchild semiconductor nc7sz86 u08, ub07 2 1.8v or adj 8-pin max/so maxim max1792eua18 u09 1 ds33r11, z44/2156 mcm 27mm x 27mm, 256-pin bga dallas semiconductor ds33r11 u10, u14 2 dsphyter ii single 10/100 ethernet transceiver (65-pin llp) national semiconductor dp83847alqa56a downloaded from: http:///
DS33R11DK/ds33zh11dk 7 of 44 designation qty description supplier/part number u11 1 ds33zh11 elite 10/100 ethernet transport over serial link 10mm x 10mm, 100-pin csbga dallas semiconductor ds33zh11 u12 1 ds21348 liu 44-pin tqfp dallas semiconductor ds21348 u13 1 ds3150 t3/e3/sts-1 liu i/f 48-pin tqfp dallas semiconductor ds3150t ub01 1 dual rs-232 transceiver with 3.3v/5v internal capacitors maxim max3233e ub02 1 ldo regulator with reset,1.20v output 300ma, 6-pin sot23 maxim max1963ezt120-t ub04, ub05 2 synchronous dram, 1meg x 32 x 4 banks, 86-pin tsop micron mt48lc4m32b2tg-7 ub06 1 high-speed buffer fairchild semiconductor nc7sz86 xb01 1 low-profile 8.0mhz crystal ecl ec1-8.000m y01, yb05 2 oscillator, crystal clock 3.3v, 2.048mhz (needs socket) saronix nth039a3-2.0480 y02 1 not populated oscillator, crystal clock 3.3v, 25.000mhz (low jitter) saronix nth089aa3-25.000 y03, yb03 2 oscillator, crystal clock 3.3v, 100.000mhz saronix nth089a3-100.0000 y04 1 spi serial eeprom 2.7v, 16k, 8-pin dip (needs socket) atmel at25160a-10pi-2.7 y05 1 oscillator, crystal clock, 3.3v, 34.368mhz (needs socket) saronix nth089aa3-34.368 yb01 1 oscillator, crystal clock 3.3v, 44.736mhz (needs socket) saronix nth089aa3-44.736 yb02 1 oscillator, crystal clock 3.3v, 1.544mhz (needs socket) saronix nth039a3-1.5440 yb04 1 oscillator, crystal clock 3.3v, 25.000mhz (low jitter) saronix nth089aa3-25.000 downloaded from: http:///
DS33R11DK/ds33zh11dk 8 of 44 system floorplan pc board errata ? center tap of t02 was not pulled to v3_3 in ds33r 11dk/ds33zh11dk01a0 revision (page 23 in schematic). pin t02.2 is pulled to v3_3 with a wire in the DS33R11DK/ds33zh11dk01a0 revision. ? reference designators were assigned for r1, r2 and r01, r02. r1 and r2 will be renamed in the next design. ? component r1, r2 and y05 are on bottom of the pc boa rd but do not have the same prefix as other components on the bottom side. ? silkscreen for j36.6 is mislabeled. it reads rt0 but should read rt1. ? oscillators y03 and yb03 are not suitab le for use as input clocks for the ethernet phy. because of this, the oscillators will only be used as the sdram oscillators. these oscillators gene rate too much jitter to function as the input clock for the phy. this requires that the phy is driven by the default oscillator, yb04 and yb02. jumpers jp03 and jp11 have been modified to prevent accidental selection of the wrong oscillator. microprocessor and serial port (57600-8-n-1) transformer and network connections (t3e3) transformer and network connections (t1e1) backplane jumpersto ds33zh11 10/100 ethernet phy and magnetics 10/100 ethernet phy and magnetics leds leds leds ds33r11 ds3150 t3e3 liu configuration jumpers ds3150 t3e3 liu configuration jumpers eeprom (config) sdram ds33zh11 tser rser tclk rclk transformer and network connections (t1e1) sdram test points test points test points ds33r11/ds33zh11 design kit ds33r11 section ds33zh11 section downloaded from: http:///
DS33R11DK/ds33zh11dk 9 of 44 file locations this design kit relies upon several supporting files, which are provided on the cd and are available as a zip file from the maxim website at www.maxim-ic.com/DS33R11DK . all locations are given relative to the top directory of the cd/zip file. table 1. ds33z11 register defi nition and configuration files file name. file usage .\ds33r11_cfg_demo_gui\ds33z11.def top level definition file to select in chipviews register mode. this file autoloads the remaining definition files shown below. (note: the ds33r11 is composed of an integrated ds33z11 and an integrated ds2155.) .\ds33r11_cfg_demo_gui\su_li_port1.def .\ds33r11_cfg_demo_gui\ds2155.def dependant files. these are called by the ds33z11.def file, which is listed above. .\ds33r11_cfg_demo_gui\basic_config.eset gui interface for loading settings when running the zchip plug-in (launched from the tools menu of the chipview program). .\ds33r11_cfg_demo_gui\basic_config.mfg .\ds33r11_cfg_demo_gui\e1_gapclk_crc4_hdb3_nocas.ini files for manually configuring the ds33z11 and ds2155 to convert ethernet traffic to serial a t1e1 stream. .\ds33r11_cfg_demo_gui\ds2155_t1_bert_esf.ini .\ds33r11_cfg_demo_gui\gapclk_llb_ds2155_t1_esf_lbo0_2.ini stand-alone configuration files for evaluating the ds33r11s integrated ds2155 t1e1 transceiver. these files are for evaluating ds2155 functionality, and disrupt the ethernet to serial traffic flow. downloaded from: http:///
DS33R11DK/ds33zh11dk 10 of 44 basic operation powering up the design kit ? connect pcb 3.3v and gnd banana plugs to power suppl y. a 2a supply is recommended. at steady-state, the system should draw approximately 700ma. ? verify that jumpers are co nfigured as described in table 2 . general ? upon power-up, the ds 33r11 queue overflow led (ds 02 red) will not be lit; also, the int led (ds01 red) will not be lit. phy link led (ds07 green) should be lit if the ethernet is connected. transceiver rlos led (ds05 red) will be lit. ? ds33zh11 does not have queue overflow or int pi ns. ds21348 and ds3150 rlos leds (ds15 and ds13 red) will be lit. following are several basic system initializations. basic ds33r11 initialization this section covers two basic methods for configuring the ds33r11. 1. device-driver based configuration. if the pins j09.4+ j09.6 are jumpered, the device driver autoconfigures the ds33r11 upon power-up. this enables traffic to pass from the ethernet port to the serial port. consult the device driver documentation for further details. 2. register-based configuration. launch chipview.exe and select register view. when prompted for a definition file, pick the file named ds33z11.def . three definition files will l oad: ds33z11 control, ds33z11 port, and ds2155 transceiver. go to the file menu and select f ile m emory config file l oad .mfg file. when prompted, select the file named basic_config.mfg . following this, load the file e1_gapclk_crc4_hdb3_nocas.ini using the menu selection f ile i nitalization config file l oad .ini file. additional configuration for ds33r11 ? using a patch cable, connect the ethernet connector to an ordinary pc, or network test equipment. this should cause the link led to turn on. ? place a loopback connector at the t1e1 network side; rlos led ds05 should go out. ? at this point any packets sent to the ds33r11 are echoed back. incoming packets (i.e., ping) should cause the rx led to blink, after which the tx led should also blink. downloaded from: http:///
DS33R11DK/ds33zh11dk 11 of 44 basic ds33zh11 initialization this section covers the eeprom methods for configuring the ds33zh11. 1) if the hwmode jumper is insta lled, the ds33zh11 will retrieve conf iguration settings from the on-board eeprom during power-up. 2) select which serial device to use: either the ds3150 t3e3 liu or the ds21348 t1e1 liu can be selected. in making this selection the backplane jumpers jp05Cjp08 must be installed to select between the two serial devices. connecting pins 2+3 of each jumper selects t he ds3150, connecting pins 1+2 of each jumper selects the ds21348. 3) configure the serial device as shown in table 2 . additional configuration for ds33zh11 ? using a patch cable, connect the ethernet connector to an ordinary pc, or network test equipment. this should cause the link led to turn on. ? place a loopback connector at the network side; the rlos led should go out. the rlos led is ds15 for t1e1 and ds13 for t3e3. ? at this point any packets sent to the ds33zh11 are echoed back. incoming packets (i.e., ping) should cause the rx led to blink, after whic h the tx led should also blink. monitor and capture ethernet traffic ? although ping is mentioned, it is not recommended. the ping command goes through the computers tcpip stack, and sometimes is not sent out the pcs network c onnector (i.e., if the pcs arp cache is out of date). additionally, ping requires two pcs, as a pc with only one adapter cannot ping itself (a local ping gets sent to a local host instead of out the connector). however, note t hat ping is still a valuable test once the prototyping stage is complete. ? generation and capture of arbitrary (raw) packets c an be accomplished using commview. a time-limited demo is available at the website www.tamos.com/pr oducts/commview . ? ethereal is an excellent (and free) packet capture utility. download at www.ethereal.com . ? adding additional ethernet ports to a pc is rather simple when a usb-to-ethernet adapter is used. this allows for end-to-end testing using a single pc. when using tw o adapters, the pc has a di fferent ip address for each adapter. test equipment allows selection of either adapter . operating system-based network traffic is sent out the default adapter. typically, this is the adapter that has recently had connection to a live network. downloaded from: http:///
DS33R11DK/ds33zh11dk 12 of 44 leds, configuration switches , jumpers, and connectors the ds33z11dk has several configuration swit ches, banana plugs, osc illators, and jumpers. table 2 provides a description of these signals, given in order of appearance on the pc board, from top to bottom then left to right (with the board held so that the rs232 connector is on the left edge). table 2. main board pc board configuration silkscreen reference function basic setting schematic page description ground (banana plug) power supply ground 2 vdd 3.3v (banana plug) power supply vdd 2 system power. always connected to power supply. connectors are provided at the top left and bottom right of board. connect either set to power supply. j01 jtag 17 jtag interface for lattice ec3 fpga. j02 rs-232 db9 connector 14 rs-232 db9 connector, operates in ascii mode at 57.6k baud, 8, n, 1. sw01 reset 12 drives reset controller u01. ds01 led 15 displays interrupt status of ds33r11 (lit when interrupt is asserted). ds02 led 7 displays queue overflow status of ds33r11 (lit when queue overflows). j04 once bdm 14 debug connector for processor. j03 flash vpp 3.3v 14 jumper for driving mmc2107 flash vpp to 5v . j05 jtag 10 jtag interface for ds2155 portion of ds33r11. j06 jtag 11 jtag interface for ds33z11 portion of ds33r11. y01 clock 11 oscillator for ds215 5 portion of the ds33r11. j07, j08 addr / dat 16 address and databus test points for ds33r11. j09 configuration pins (see next two rows for details.) schematic page16 configuration switches for selecting device driver behavior. additional detail given below. j09.2+j09.4 removed not installed pin j09.2 has been removed. jumpering this pin to j09.4 causes a conflict with j09.6 fpga pin. j09.4+j09.6 driver enable installed enables device driver and interrupt handler when jumper is installed. j09.8+j09.10 rclk select (fpga) user selection causes device to select serial link tclk = rclk when jumpered. when not jumpered tclk = mclk. y02 ethernet phy clock 3 25.000mhz clock for ds33r11 ethernet phy. jp03 clock select pins 1+2 jumpered 3 must be set with pins 1+2 jumpered. sdram oscillator does not meet jitter requirement of the ethernet phy. j10 jumper installed 10 connects ds33r11 receive serial lines. j11 jumper installed 10 connects ds33r11 transmit serial lines. downloaded from: http:///
DS33R11DK/ds33zh11dk 13 of 44 silkscreen reference function basic setting schematic page description jp01 3-pin jumper pins 2+3 jumpered 10 drives ds33r11 tden pin to vcc. jp02 3-pin jumper pins 2+3 jumpered 10 drives ds33r11 rden pin to vcc. j18 test points pins 9+10 and 5+6 jumpered 10 test points, connecting rclk and tclk to channel clock pins of transceiver. j12, j13 test points 11 test points for integrated transceiver of ds33r11. j14, j15, j16 jumpers not installed 4 installation forces ethernet phy mode. when not installed the phy autonegotiates its settings. ds06, ds07, ds08 led 4 activity leds for ethernet phy. tx lights when phy sends a packet; link lights when the phy has found a link partner. ds10, ds11, ds09 led 4 ethernet phy mode leds. used for display of speed, duplex, and collision. j21 lan network connection 5 rj45 connector for ethernet phy. j22, j23 test points 4 test points for mii interface between phy and ds33r11. j19, j20 j24 wan network connection 11 t1e1 coax and rj45 connectors for network. j17, j25 jumper not installed 11 connects adjacent coax connector to ground. y03 clock 10 100mhz sdram clock for ds33r11. j28 configuration pins (see next 10 rows for details.) schematic page 23 pin bias for ds3150. when not jumpered, this pin is pulled to ground, jumper drives pin to vcc. a basic description of the pin function is given below. refer to the data sheet for full detail. j28.20 ds3150 pin (zcse) not installed 0 = b3zs/hdb3 encoder/decoder enabled (nrz interface enabled) 1 = b3zs/hdb3 encoder/decoder disabled (bipolar interface enabled) j28.18 ds3150 pin (tts) installed 0 = tri-state the transmit output driver, disable the jitter attenuator in the transmit path 1 = enable the transmit output driver, disable the jitter attenuator in the transmit path j28.16 ds3150 pin (tess) installed 0 = e3 1 = t3 (ds3) j28.14 ds3150 pin (tds1) not installed j28.12 ds3150 pin (tds0) not installed 00=transmit normal data clocked in on tpos/tnrz and tneg 11=transmit prbs j28.10 ds3150 pin (rmon) not installed 0 = disable the monitor preamp, disable the jitter attenuator in the receive path 1 = enable the monitor preamp, disable the jitter attenuator in the receive path j28.8 ds3150 pin (lbks) installed 0 = analog loopback enabled 1 = no loopback enabled j28.6 ds3150 pin (lbo) installed 0 = cable length 225ft 1 = cable length < 225ft downloaded from: http:///
DS33R11DK/ds33zh11dk 14 of 44 silkscreen reference function basic setting schematic page description j28.4 ds3150 pin (ice) 0 = normal rclk/normal tclk: update rpos/rnrz and rneg/rlcv on falling edge of rclk; sample tpos/tnrz and tneg on rising edge of tclk 1 = normal rclk/inverted tclk: update rpos/rnrz and rneg/rlcv on falling edge of rclk; sample tpos/tnrz and tneg on falling edge of tclk j28.2 ds3150 pin (efe) not installed 0 = enhanced features disabled 1 = enhanced features enabled jp09 clock selection pins 3+2 jumpered 23 selects ds3150 mclk. jumper pins 1+2 for mclk = rclk; jumper pins 3+2 for mclk = osc_yb01. ds12, ds13, ds14 led 23 ds3150 leds for prbs, los and dm. j38, j39 bnc 23 ds3150 bnc network interface. jp05Cjp08 serial backplane user config 18 jumper pins 1+2 to select ds21348 t1e1, jumper pins 2+3 to select ds3150. j29 configuration pins (see next 10 rows for details.) pin bias for ds21348. when not jumpered, this pin is pulled to ground, jumper drives pin to vcc. a basic description of the pin function is given below. refer to the data sheet for full details. j29.1 ds21348 pin (cs_egl) 0 = -12db (short haul) 1 = -43db (long haul) j29.3 ds21348 pin (rd_ets) 0 = e1 1 = t1 j29.5 ds21348 pin (wr_nrz) 0 = bipolar data at rpos/rneg and tpos/tneg 1 = nrz data at rpos and tpos or tneg; rneg outputs a positive-going pulse when device receives a bpv, cv, or exz j29.7 ds21348 pin (ale/sclke) 0 = disable 2.048mhz synchronization transmit and receive mode 1 = enable 2.048hz synchronization transmit and receive mode j29.9 ds21348 pin (vsm) should be tied low for 3.3v operation. j29.11 ds21348 pin (lo) transmit liu waveshape select bits. (refer to the ds21348 data sheet table 7-1 and 7-2.) j29.13 ds21348 pin (dja) 0 = jitter attenuator enabled 1 = jitter attenuator disabled j29.15 ds21348 pin (jamux) e1 (ets = 0) jamux mclk = 2.048mhz 0 t1 (ets = 1) mclk = 2.048mhz 1 mclk = 1.544mhz 0 j29.17 ds21348 pin (jas) 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side j29.19 ds21348 pin (hbe) schematic page 25 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) downloaded from: http:///
DS33R11DK/ds33zh11dk 15 of 44 silkscreen reference function basic setting schematic page description j31 configuration pins (see next 10 rows for details) pin bias for ds21348. when not jumpered, this pin is pulled to ground, jumper drives pin to vcc. a basic description of the pin function is given below. refer to the data sheet for full details. j31.1 ds21348 pin (mm1) j31.3 ds21348 pin (mm0) monitor mode selection. see table 2-11 in the ds21348 data sheet. j31.5 ds21348 pin (loop1) j31.7 ds21348 pin (loop0) loop 1, loop 0: 11 = rlb 10 = llb 01 = alb j31.9 ds21348 pin (tx1) j31.11 ds21348 pin (tx0) transmit data control (pattern vs. tpos/tneg) j31.13 ds21348 pin (tpd) 0 = normal transmitter operation 1 = powers down the transmitter and tri-states the ttip and tring pins j31.15 ds21348 pin (ces) 0 = update rneg/rpos on rising edge of rclk; sample tpos/tneg on falling edge of tclk 1 = update rneg/rpos on falling edge of rclk; sample tpos/tneg on rising edge of tclk j31.17 ds21348 pin (test) set high to tri-state all outputs and i/o pins. j31.19 ds21348 pin (pbts/rt0) schematic page 25 selects receive termination in conjunction with rt1. j36 configuration pins (see next three rows for details.) pin bias for ds21348. when not jumpered, this pin is pulled to ground, jumper drives pin to vcc. a basic description of the pin function is given below. refer to the data sheet for full details. j36.2 ds21348 pin (l1) transmit liu waveshape select bits. (refer to the ds21348 data sheet table 7-1 and 7-2.) j36.4 ds21348 pin (l2) transmit liu waveshape select bits. (refer to the ds21348 data sheet table 7-1 and 7-2.) j36.6 ds21348 pin (rt1) the silkscreen on this pin is mislabeled. should read rt1 with a function of selecting receive termination. jp10 clock selection 25 ds15 led 25 j40, j41 network connection 24 j27 ds33zh11 pin (modec1) 21 j26 ds33zh11 pin (hwmode) 21 jpb01 jumper 21 j30, j33 test points schematic page 25 26 test points for mii interface between phy and ds33zh11. jp11 clock selection pins 2+3 jumpered 18 must be set with pins 1+2 jumpered. sdram oscillator does not meet jitter requirement of the ethernet phy. j32, j35, j34 jumpers not installed 26 installation forces ethernet phy mode. when not installed, the phy autonegotiates its settings downloaded from: http:///
DS33R11DK/ds33zh11dk 16 of 44 silkscreen reference function basic setting schematic page description ds19, ds20, ds21 led 19 activity leds for ethernet phy. tx lights when phy sends a packet; link lights when the phy has found a link partner. ds16, ds17, ds18 led 19 ethernet phy mode leds. used for display of speed, duplex, and collision. sw02 reset button 19 ground (banana plug) power supply ground 2 redundant power supply connection (see top left of board). vdd 3.3v (banana plug) power supply vdd 2 redundant power supply connection (see top left of board). yb01 ds3150 mclk 23 44.736mhz, for use with ds3150 in t3 mode (bottom side of pc board) yb02 ds21348 mclk 25 1.544mhz, for use with ds21348 in t1 mode (bottom side of pc board) yb04 ethernet clock 18 25.000mhz driver for ds33zh11 ethernet phy (bottom side of pc board). yb03 sdram clock 21 100mhz sdram clock for ds33zh11 (bottom side of pc board). yb05 spare oscillator 25 2.048mhz, for use with ds21348 in e1 mode (bottom side of pc board). y05 spare oscillator 23 34.368mhz for use with ds3150 in e3 mode (bottom side of pc board). address map (all cards) the external device address space begins at 0x81000000. all offsets given below are relative to this offset. table 3. overview of daughter card address map offset device description 0x0000 to 0x0087 fpga processor board identification 0x1000 to 0x1fff ds33r11 ethernet to serial engine. uses cs_x1. 0x4000 to 0x4fff ds33r11 t1e1 portion of ds33r11. uses cs_x4. registers in the ds33r11 can be easily modified using th e chipview host-based user-interface software with the definition files previously mentioned. ds33r11 information for more information about the ds33r11, refer to the ds33r11 data sheet available on our website at www.maxim-ic.com/ds33r11 . downloaded from: http:///
DS33R11DK/ds33zh11dk 17 of 44 DS33R11DK/ds33zh11dk information for more information about the DS33R11DK/ds33zh11dk, including software downloads, refer to the data sheet available on the our website at www.maxim-ic.com/DS33R11DK . technical support for additional technical support, go to www.maxim-ic.com/support . schematics the ds33r11/ds33zh11dk schematics are featured in the fo llowing pages. as this is a hierarchal schematic some explanation is in order. the board is composed of two top-level hierarchal blocks: the ds33r11 block and the ds33zh11, both of thes e are nested hierarchy blocks. the ds33r11 hierarchy block contains individual hierarchy blocks for the ethernet phy, ds33r11 and mi croprocessor portions of the design. the ds33zh11 hierarchy block contains individual hierarchy blocks for the ethernet phy, ds33zh11, t1e1 liu, and the t3e3 liu portions of the design. all signals inside a hierarchy block are local, with exception for v cc and ground. in-port and out-port connectors are used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. from here blocks are wired together as if they were ordina ry components. the system diagram is shown again below, with schematic page numbers given for each functional block. ds21348 liu block page 18 symbol schematic pages 24-25 ethernet phy page 3 symbol schematic pages 04-05 ds3150 liu block page 18 symbol schematic page 23 ethernet phy page 18 symbol schematic pages 26-27 ds33zh11 block page 18 symbol schematic pages 20-22 ds33zh11 block page 3 symbol schematic pages 06-11 p block page 3 symbol schematic pages 12-17 ds33r11 section page 1 top level of design contains 34 hierarchy blocks schematic pages 18-27 ds33r11 section page 1 top level of design contains 3 hierarchy blocks schematic pages 03-17 ds33rzh11 pc board layout & schematic hierarcy block page listing downloaded from: http:///
page 01: ds33r11 and ds33zh11 design top level hierarchy blocks page 03: hierarchy blocks for ds33r11, processor and ethernet only signals with import/outport connectors have connection outside the pages 18-19: hierarchy blocks for ds33zh11, ethernet and serial (wan) interface pages 04-05: ethernet physical interface (phy) pages 06-11: ds33r11 pages 12-17: processor card pages 20-22: ds33zh11 page 23: ds3150 line interface unit (liu) pages 24-25: ds21348 line interface unit (liu) pages 26-27: ethernet physical interface (phy) ds33zh11 top level hierarchy block pages 18-27 hierarchy block pages 03-17 ds33r11 top level notes: each hierarchy block is independent of the next. page 02: decoupling / mounting holes ds33zh11 design ds33r11 design: contents hierarchy block. these signals appear as pins on the hierarchy block connector printed fri sep 23 11:01:48 2005 block name: _ztopdn_. parent block: 01/05/2005 1/2(block) 1/27(total) steve scully ds33zh11-r11dk01a0 fpga_zhspics fpga_zhspisck fpga_zhmiso fpga_zhmosi fpga_spics zmiso zspisck zmosi page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 _ds33zh11dk_design zmosi zspisck zmiso fpga_spics _DS33R11DK_design fpga_zhmosi fpga_zhmiso fpga_zhspisck fpga_zhspics downloaded from: http:///
ground testpoints 2/2(block) steve scully ds33zh11-r11dk01a0 2/27(total) 01/05/2005 block name: _ztopdn_. parent block: b a b a b a b a 2 1 jb05 2 1 jb02 2 1 jb01 2 1 jb04 cb151cb175 cb74cb125 cb127 2 1 c14 1 h03 1 h04 1 hb01 1 h01 1 hb03 1 h02 1 h05 1 hb02 1 h06 1 2 db01 2 1 cb58 2 1 cb64 2 1 cb131 2 1 cb22 2 1 cb20 2 1 cb54 2 1 c03 2 1 cb47 2 1 cb48 2 1 c17 2 1 c20 2 1 cb132 2 1 cb62 2 1 c22 2 1 cb32 2 1 cb19 2 1 cb28 2 1 cb59 2 1 cb60 2 1 cb124 2 1 cb61 2 1 cb21 2 1 cb27 2 1 cb30 2 1 cb31 2 1 cb10 2 1 cb139 2 1 cb38 2 1 cb118 2 1 cb140 2 1 cp01 2 1 cp02 2 1 cp03 2 1 c01 2 1 c28 2 1 cb136 2 1 cb03 c19 cb52cb100 c16c18 c12 c08 cb51 cb17 c09 cb75cb50 cb06 cb18 cb01 cb149cb150 cb134 cb133 cb53 cb57 cb55 cb107 cb16 cb13 cb116 cb09 cb15 cb35 cb14 cb34 cb05 cb04 cb46cb138 cb02 cb143 cb142 c23 cb141cb07 cb147 cb39 cb11 c21 c24 cb145cb144 cb08 cb137 cb135 1 gnd_tpp05 1 gnd_tpp04 1 gnd_tpp03 1 gnd_tpp02 1 gnd_tpp09 1 gnd_tpp08 1 gnd_tpp07 1 gnd_tpp06 1 gnd_tpb01 1 gnd_tpp13 1 gnd_tpp12 1 gnd_tpp11 1 gnd_tpp10 1 gnd_tp02 1 gnd_tpp16 1 gnd_tpp15 1 gnd_tpp14 1 gnd_tpp20 1 gnd_tpp19 1 gnd_tp03 1 gnd_tpp18 1 gnd_tpp17 1 gnd_tpp21 1 gnd_tpp22 1 gnd_tp01 1 gnd_tpp23 1 gnd_tpp01 10uf.1uf red black black red 10uf 470uf 1.00standoff_nut 10uf 10uf 0.1uf0.1uf 0.1uf 0.1uf0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 10uf 10uf10uf 0.1uf 0.1uf 10uf 1 1 10uf 1 1 1.00standoff_nut 10uf10uf 10uf10uf 10uf 10uf 10uf 0.1uf 0.1uf0.1uf 0.1uf 10uf 470uf 470uf 10uf10uf 470uf470uf 470uf 10uf10uf 10uf10uf 10uf 10uf 10uf 10uf 10uf10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 470uf 10uf 10uf 10uf 10uf 10uf10uf 10uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 10uf10uf 10uf 10uf 10uf 10uf.1uf page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 conn_banana_2p a b conn_banana_2p a b conn_banana_2p a b v3_3 conn_banana_2p a b v3_3 4 4 4 4 4 4 4 4 4 v3_3 v3_3 v3_3 downloaded from: http:///
pages 12-17 pages 04-05 pages 06-11 processor hierarchy block r11 hierarchy block mii ethernet hierarchy block ds33r11 design kit page numbers (bottom right) are listed by both the page number in the block, and by the page number within the entire design notes: all hierarchy block names end in _dn. pins on hierarchy blocks do not have pin numbers (but pins on symbols do). signals inside a hierarchy block are local to that block - the signal temp in block_a_dn is different than temp in block_b_dn. cross reference indicators are referenceing a given net to other pages in the design (page number given is according to entire design, not the current block) ds33zh11-r11dk01a0 01/05/2005 steve scully block name: _DS33R11DK_design. parent block: \_ztopdn_\ 3/27(total) 1/1(block) printed sat sep 17 15:05:43 2005 txd0 mii_clk mdc mdio txd1txd2 txd3 tx_clk rxdv col_det rx_crsrx_err rx_clk led_dplx_add0 led_col_add1 led_gdlink_add2 led_rx_add4 led_tx_add3 rxd0rxd3 rxd2 rxd1 tx_en reset cs_ethcs_ser rd dat<7..0> addr<9..0> ref_clk_in mdio rst_serial rst_eth col_det txd0 wr tx_en int rxd0rxd1 rxd2 rxd3 rx_clkrx_crs rx_err rxdv txd1 ref_clko_pn txd2txd3 tx_clk mdc fpga_zhspisck fpga_zhspics fpga_zhmosi reset rd_dutwr_dut int3 cs_x1cs_x2 cs_x5 int4int5 cs_x3cs_x4 d_dut<7..0> reset_ah int2 a_dut_<9..0> fpga_zhmiso reset tx_en rxd1rxd2 rxd3 rxd0 led_tx_a3led_rx_a4 led_gdlink_a2 led_col_a1 led_dplx_a0 rx_clkrx_err rx_crscol_det rxdvtx_clk txd3 txd2 txd1 mdiomdc txd0 i25 dat<7..0> y02 jp03 r04 r05 ds08 ds06 rb57 rb68 ds07 rb66 rb55 rb67 ds09 rb56 rb75 rb72 ds11 rb71 rb76 fpga_zhmosi fpga_zhspics fpga_zhspisckfpga_zhmiso addr<9..0> wr rd cs_eth int i28 i34 rst_serial reset ref_clkoref_clk_in mdc reset mdio cs_ser i32 npop-25.000mhz_3.3v i30 30 30 1 i20 amber 5.1k 1 led_gdlink_a2 5.1k 1 1 330 amber 1 5.1k 1 330 1 1 1 amber 1 330 5.1k 1 1 330 green 330 1 5.1k 1 1 red led_dplx_a0 led_col_a1 led_tx_a3 led_rx_a4 gnd v3_3 i4 i11 i15 i19 i21 i22 1 2 1 2 1 2 1 2 1 3 2 1 8 4 5 1 2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in out out out _motprocrescard_dnfpga_zhmiso a_dut_<9..0> int2 reset_ah d_dut<7..0> cs_x4 cs_x3 int5 int4 cs_x5 cs_x2 cs_x1 int3 wr_dut rd_dut reset fpga_zhmosi fpga_zhspicsfpga_zhspisck vcc 1 osc gnd out v3_3 _z11andlan_dn mdc tx_clk txd3 txd2 ref_clko_pn txd1 rxdv rx_err rx_crs rx_clk rxd3 rxd2 rxd1 rxd0 int tx_en wr txd0 col_det rst_eth rst_serial mdio ref_clk_in addr<9..0> dat<7..0> rd cs_ser cs_eth _mii_wan_dn reset tx_en rxd1rxd2 rxd3 rxd0 led_tx_add3led_rx_add4 led_gdlink_add2 led_col_add1 led_dplx_add0 rx_clkrx_err rx_crs col_det rxdv tx_clk txd3 txd2 txd1 mdio mdc mii_clk txd0 v3_3 v3_3 downloaded from: http:///
beginning of mii ethernet hierarchy block placement note: leds need to be attached outside of module due to be placed close to pin c1 and rbias must componets for testpoints (shown above) must be placed the same for each port to 0.2 between connectors. allow use of a different phy card if desired. placement should allow on z44 card all 4 ports must be placed with equal spacing and a common center line strap adapting option of dp83847 analog supply caps to be placed close to pin 14 of phy block name: _mii_wan_dn. parent block: \_DS33R11DK_design\ 4/27(total) printed fri sep 23 11:01:50 2005 ds33zh11-r11dk01a0 steve scully 01/05/2005 1/2(block) reserved12reserved13 reserved16 reserved17 reserved18 gnd1gnd2 gnd3 gnd4 gnd5 reserved10reserved11 reserved4reserved5 reserved6 reserved7 reserved8 reserved9 vdd/io_vdd1vdd/io_vdd2 vdd/ana_vdd vdd1vdd2 vdd3 reserved2reserved1 rbias reset* c1 x2 x1 an_0 an_1 an_en led_speed led_rx/phyad4 led_col/phyad1 led_dplx/phyad0 mdio mdc reserved3 led_gdlnk/phyad2 led_tx/phyad3 reserved15 reserved14 0.1uf cm98 cm32 0.1uf cp15 0.1uf cm82 cp09 10uf an0 an1 an_en ? amber cm77 an_v3_3 cp08 cm75 cm29 cm89 jp24 jp25 rm36 rm35 rm34 tpp01 rm24 tpp02 rp11 up15 cp07 cm78 rm02 led_dplx_add0 led_tx_add3 10uf 10.0k reset 0.1uf mii_clk led_col_add1 led_rx_add4 rbias an_v3_3 330 1 c1pin 0.1uf 0.1uf 5.1k tx_en tx_clk col_det rx_crs rxd3 rxd2 rxd1 rx_clk rx_err rxd0 rxdv 5.1k mdc mdio 30 txd1txd0 txd3txd2 0.1uf 0.1uf 10uf cp17 10uf 10uf 0.1uf cm67 led_speed<1> led_gdlink_add2 5.1k jmp_2 jmp_2 jmp_2 1 ? ? page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 io v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p v3_3 out out out out out out out out out 6 10 8 4 1 2 3 5 7 9 conn_10p in out in in in v3_3 in in in control dp83847_u1 reserved14reserved15 led_tx/phyad3 led_gdlnk/phyad2 reserved3 mdc mdio led_dplx/phyad0 led_col/phyad1 led_rx/phyad4 led_speed an_en an_1an_0 x1 x2 c1 reset* rbias reserved1 reserved2 vdd3 vdd2 vdd1 vdd/ana_vdd vdd/io_vdd2 vdd/io_vdd1 reserved9 reserved8 reserved7 reserved6 reserved5 reserved4 reserved11 reserved10 gnd5 gnd4 gnd3 gnd2 gnd1 reserved18 reserved17 reserved16 reserved13 reserved12 v3_3 io io io io io in downloaded from: http:///
resistors for td+-/rd+- should be placed close to xfrm should be placed close to phy end of mii ethernet hierarchy block caps for xfrm center tap block name: _mii_wan_dn. parent block: \_DS33R11DK_design\ 5/27(total) 2/2(block) steve scully ds33zh11-r11dk01a0 01/05/2005 sh1 p2p8 p6 p3 p4 sh2 p1 p5 col txd<2>rd+ rd- rxd<3> txd<3> rx_clk rxd<1> rxd<0>rxd<2> td- td+ crs/led_cfg* tx_clk tx_ertx_en txd<0> txd<1> rx_dv rx_er/pause_en* 30 rxd0 49.9 td_n .1uf .1uf rxdv td_p td_n rd_n rd_p col_det rx_crs 3030 rxd3 rxd2 rxd1 30 49.9 54.9 54.9 .1uf rd_n td_p rd_p sym_1 txd3 30 30 txd2 txd1 txd0 tx_en rx_err 30 30 tx_clk rx_clk up15 cm59 jp21 rm10 cp12 rm06 rm21 rm03 rp08 rm05rm08 rp06 rm13rm09 cm63 rm12rm14 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 port dp83847_u1 rx_er/pause_en* rx_dv txd<1> txd<0> tx_en tx_er tx_clk crs/led_cfg* td+td- rxd<2> rxd<0>rxd<1> rx_clk txd<3>rxd<3> rd- rd+ txd<2> col v3_3 conn_hfj11_2450_u j1 j2j3 j6 j4,5j7,8 p5 p1 sh2 p4p3 p6 p8 p2 sh1 downloaded from: http:///
beginning of ds33r11 hierarchy block ds33zh11-r11dk01a0 steve scully 1/6(block) 6/27(total) 01/05/2005 block name: _z11andlan_dn. parent block: \_DS33R11DK_design\ rclk a<6>a<9> a<8> tser a<3>a<5> a<7> d<0> d<6> d<5> d<4> a<4> tchblk tpositposo tnego teso tdata bpclk rchclk rchblk mclk jtdi tchclk rserrsig rsigf rfsync rlos/ltc rmsync rnegirnego rposi rposo rsysclk rtip rring tring1 tring2 ttip1ttip2 rcl liuc rclkirclko rdata d<2>d<3> tnegi d<7> d<1> a<2> tsysclk jtclk wr* 8xclk ser_cs* xtald tstrst test1test2 jtrst tsig rsync tsync tssync tclko tclki tclk rd* jtms eth_cs* int* a<1> a<0> jtdo spi_cs tpb07 2 1 ds05 rb48 tpb09tpb08 j4 c11 r2 r1 e4 c1 c4a5 b4 e3 t2 t1 e1 b3 d3 c3 d6 c6d4 a4 c2 d1 d2 g1 a2 a9 d7 k1 f4 g4 p3 l3 h2 m1 n3 j3 n2 l4 u3 n1 a3 h3 b11 m3 m4 g3 b5g2 a1 h4 b2 b8 b9 c5 b6 a6 a10 a11 b12 a12 c13 b13 a13 c14 b14 a14 b1 c15 c16 b16 a16 c17 b17 a17 c18 b18 a18 k4 u09 int s_rlos s_rlos zspics s_jtdo cs_eth s_jtms rd s_tclks_tclki s_tclkos_tssync s_tsync s_rsync s_tsig s_jtrst rst_serial cs_ser s_8xclk wr s_jtclk s_tsysclk s_tnegi s_rdata s_rclko s_rclki s_liucs_rcl rring rtip s_rsysclk s_rposo s_rposi s_rnego s_rnegi s_rmsync s_rfsync s_rsigf s_rsig s_rser s_tchclk s_jtdis_mclk s_rchblks_rchclk s_bpclks_tnego s_tposo s_tposi s_tchblk s_tser s_rclk 3 2 1 ttip 7 0 58 6 4 7 9 1 2 3 45 6 0 addr<9..0> dat<7..0> 330 red s_tdata s_teso tring page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in in control & transceiver port ds33r11_u1 spi_cs jtdo a<0>a<1> int* eth_cs* jtms rd* tclktclki tclko tssync tsyncrsync tsig jtrst test2 test1 tstrst xtald ser_cs* 8xclk wr* jtclk tsysclk a<2>d<1> d<7> tnegi d<3> d<2> rdata rclko rclki liuc rcl ttip2 ttip1 tring2 tring1 rring rtip rsysclk rposo rposi rnego rnegi rmsync rlos/ltc rfsync rsigf rsig rser tchclk jtdimclk rchblkrchclk bpclktdata teso tnego tposo tposi tchblk a<4>d<4> d<5> d<6> d<0> a<7> a<5> a<3> tser a<8>a<9> a<6> rclk out inin in io in downloaded from: http:///
steve scully 7/27(total) block name: _z11andlan_dn. parent block: \_DS33R11DK_design\ 01/05/2005 2/6(block) ds33zh11-r11dk01a0 zjtclk rden0 rser0 tclki0 tden0 rclki0 tser0 h10s0 hwmode rst* rmiis modec0 modec1 afcs col0crs0 refclk refclko rxerr0 rxdv0 qovf swe* zjtdi sdata<27>sdata<28> sdata<29> sdata<30> sdata<26> sdata<25> sdata<24> sdata<23> sdata<22> sdata<21> sdata<20> sdata<19> sdata<18> sdata<17> sdata<16> sdata<15> sdata<14> sdata<13> sdata<12> sdata<11> sdata<10> sdata<9> sdata<8> sdata<7> sdata<6> sdata<5> sdata<4> sdata<3> sdata<1> rxd0_3 rxd0_1 rxd0_0rxd0_2 rxclk0 zjtdo sdata<31> sda<3>sda<4> sda<5> sda<6> sda<7> sda<9> sda<8> sda<10>sda<11> sda<2> sda<1> sda<0> sras sba0sba1 scas* scs* sdclki sdclko stenstmd smask1 smask3 smask2 txclk0 txd0_1 txd0_3smask0 txd0_2 txd0_0 sdata<0>sdata<2> mdio mdc txen0 zjtms zjtrst* fullh0 dcedte r03 1 tp01 rb20 ds02 c7 c8 b7 c9 a7 f20 e19 e20 f18 f19 h19 e2 d5 f1 w10 e18 d18 w9 v15 v16 v7 y6 y8 v8 w16 w17 v17 w19 y18 t20 t19 u20 w20 u19 y20 v19 y19 v18 y17 y16 w1 w3 v1 v3 v2 v4 w4 v6 w6 v5 w5 y3 y5 y2 y4 w2 w11 v14 y10 v12 y12 w13 v13 y14 w15 y15 w12 w14 v10 w7 v11 y11 k18k19 m18 l20 l19 l18 m20 a8 h1 g19 a20 a19 p2f2 h18 b20b19 c20 c19c10 n20 n19 g20 m19 n18 k20 u09 rb70 rb96rb77 rb80 rb82 rb81 rb79 sd_clko sd_we sd_ras tx_clk dcedtes fullds z_jtrst z_jtms mdc sd_dqm0sd_dqm2 sd_dqm3 sd_dqm1 scanmod scanen sd_clki sd_cs sd_cas sd_ba1 sd_ba0 z_jtdo rx_clk rxd2 rxd0rxd1 rxd3 z_jtdi qovf rxdv rx_err ref_clko_pn ref_clk_in rx_crs col_det afcs modec1modec0 rmiimiis hwmode h10s z_rclki z_tden z_tclki z_rser z_rden z_jtclk qovf 330 txd2 sd_a<11..0> rst_eth 30 txd3 txd1 txd0 30 0 1 3 24 6 58 7 9 10 11 31 30 29 28 27 26 25 24 23 22 21 20 30 1 0 30 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 2 3 4 z_tser sd_dq<31..0> 30 30 tx_en mdio page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in io out in out in in in in in in in in in in out outout out out ethernet to serial engine ds33r11_u1 dcedtefullh0 zjtrst* zjtms txen0 mdc mdio sdata<2> sdata<0> txd0_0txd0_2 smask0 txd0_3 txd0_1 txclk0smask2 smask3 smask1 stmd sten sdclko sdclki scs* scas* sba1 sba0sras sda<0>sda<1> sda<2> sda<11> sda<10> sda<8>sda<9> sda<7> sda<6> sda<5> sda<4> sda<3> sdata<31> zjtdo rxclk0rxd0_2 rxd0_0 rxd0_1 rxd0_3 sdata<1>sdata<3> sdata<4> sdata<5>sdata<6> sdata<7> sdata<8> sdata<9> sdata<10> sdata<11> sdata<12> sdata<13> sdata<14> sdata<15> sdata<16> sdata<17> sdata<18> sdata<19> sdata<20> sdata<21> sdata<22> sdata<23> sdata<24> sdata<25> sdata<26> sdata<30> sdata<29> sdata<28> sdata<27> zjtdi swe* qovf rxdv0 rxerr0 refclko refclk crs0 col0afcs modec1 modec0 rmiis rst* hwmode h10s0 tser0 rclki0 tden0 tclki0 rser0rden0 zjtclk downloaded from: http:///
from z11 sysclko synchronous dram mt48lc4m32b2 - 1 meg x 32 x 4 banks block name: _z11andlan_dn. parent block: \_DS33R11DK_design\ ds33zh11-r11dk01a0 steve scully 3/6(block) 01/05/2005 8/27(total) vdd4vdd3 vddq6vddq1 clkcs* cke cas* we* dqm<0> ras* dqm<1>dqm<2> dqm<3> ba<0>ba<1> a<0>a<1> a<3> a<2>a<4> a<6> a<5>a<8> a<7>a<9> a<10>a<11> dq<5>dq<6> dq<7> dq<8> dq<9> dq<10> dq<11> dq<12> dq<14> dq<13>dq<15> dq<16> dq<17> dq<18> dq<20> dq<19>dq<21> dq<23> dq<22>dq<25> dq<24>dq<26> dq<27> dq<28> dq<29> vddq5vddq4 dq<4> vdd2vdd1 dq<2>dq<3> dq<1>dq<0> dq<30>dq<31> vssq8 vssq6 vssq7vssq5 vssq3 vssq4vssq1 vssq2 vss3 vss4vss1 vss2 vddq7 vddq8vddq3 vddq2 17 84 78 5246 3832 12 6 86 72 5844 81 75 5549 41 35 9 3 4329 15 1 19 59 28 71 16 56 54 53 51 50 48 47 45 42 40 39 37 36 34 33 31 85 83 82 80 79 77 76 74 13 11 10 8 7 5 42 20 6867 18 23 22 21 24 66 65 64 63 62 61 60 27 26 25 ub04 sd_cssd_we sd_ba1 sd_ba0 sd_ras sd_cas sd_dqm3 sd_dqm2 sd_dqm1 sd_dqm0 sd_clko sd_a<11..0> 10 sd_dq<31..0> 8 7 6 5 4 29 28 27 26 25 24 23 22 3 21 20 19 18 17 16 15 14 13 2 12 11 10 9 8 6 7 5 4 3 1 2 30 31 1 0 11 9 0 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 mt48lc4m32b2_tsop_u vddq2 vddq3 vddq8vddq7 vss2vss1 vss4vss3 vssq2 vssq1 vssq4vssq3 vssq5 vssq7vssq6 vssq8 dq<31> dq<30> dq<0> dq<1> dq<3> dq<2> vdd1 vdd2 dq<4> vddq4 vddq5 dq<29> dq<28> dq<27> dq<26> dq<24>dq<25> dq<22>dq<23> dq<21> dq<19>dq<20> dq<18> dq<17> dq<16> dq<15> dq<13>dq<14> dq<12> dq<11> dq<10> dq<9> dq<8> dq<7> dq<6> dq<5> a<11> a<10> a<9> a<7>a<8> a<5>a<6> a<4> a<2>a<3> a<1> a<0> ba<1> ba<0> dqm<3> dqm<2> dqm<1> ras* dqm<0> we* cas* ckecs* clk vddq1 vddq6 vdd3 vdd4 v3_3 downloaded from: http:///
01/05/2005 steve scully ds33zh11-r11dk01a0 block name: _z11andlan_dn. parent block: \_DS33R11DK_design\ 4/6(block) 9/27(total) rst shdn in outgnd set out in vss7vss8 vss9 vss10 vss11 vss12 vss13 vss14 vss15 vss17 vss16vss18 vss19 vss20 vss21 vss22 vss23 vss24 vss25 vss26 vss27 1.8vdd81.8vdd9 1.8vdd31.8vdd6 1.8vdd7 1.8vdd5 1.8vdd101.8vdd12 1.8vdd11 1.8vdd13 dvdd1dvdd3 dvdd2dvdd4 dvdd5 dvdd6 dvdd7 dvdd8 3vdd16 3vdd15 3vdd14 3vdd13 3vdd12 3vdd11 3vdd10 3vdd9 3vdd8 3vdd7 3vdd6 3vdd5 3vdd4 3vdd3 3vdd2 3vdd1 tvdd rvdd2 rvdd1 vss6 vss4vss5 vss1vss2 vss3 tvss3 tvss2 tvss1 rvss5 rvss4 rvss3 rvss1rvss2 dvss1dvss2 dvss3 dvss4 tvss4 1.8vdd4 1.8vdd2 1.8vdd1 2 1 cb103 2 1 cb123 2 1 cb66 2 1 cb108 2 1 cb96 2 1 cb111 2 1 cb112 cb68cb85 cb129 cb99 cb130 2 1 cb120 2 1 cb109 2 1 cb117 2 1 cb97 2 1 cb82 2 1 cb121 2 1 cb88 2 1 cb92 2 1 cb83 2 1 cb70 2 1 cb80 2 1 cb49 2 1 cb69 2 1 cb101 2 1 cb113 2 1 c04 2 1 cb71 2 1 cb86 2 1 cb115 2 1 cb94 2 1 cb110 2 1 cb146 2 1 cb93 2 1 cb90 2 1 cb114 2 1 cb102 2 1 cb104 2 1 cb128 2 1 cb81 2 1 cb79 2 1 cb106 2 1 cb73 2 1 cb84 cb148cb67 cb98 cb63 cb119 cb89 u8 p20 u7 u9 u6 u5 u4 u16 u15 u14 a15 u13 u12 d19 j19 w18 h20 u11 u10 d9 d8 d10 u18 v20 y1 w8 y7 u2 t3 r3 p1 u1 m2 l2 j1 k2 j2 k3 l1 t4 r4 p4 n4 d14 d13 d12 d11 d15 d17 d16 e17 l17 m17 t18 n17 p17 k17 r17 t17f17 r18 g17 d20 g18 h17 j17 u17 y13 p18 r20 p19 v9 j20 f3 b10r19 j18 c12 y9 b15 u09 1 2 cb45 2 1 cb36 2 1 cb42 2 1 cb43 5 4 8 7 3 2 6 1 u08 1 2 cb44 1 2 cb37 1 2 cb40 1 2 cb41 10uf 0.1uf 10uf 0.1uf 1uf v1_8zchip v1_8zchip 10uf10uf 10uf 0.1uf0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 470uf 0.1uf0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 470uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 10uf10uf 10uf 10uf 10uf 10uf 1uf1uf 1uf 1uf 10uf 1uf 1uf 0.1uf0.1uf 0.1uf 0.1uf0.1uf 0.1uf v1_8zchip 0.1uf page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 power & ground ds33r11_u1 1.8vdd11.8vdd2 1.8vdd4 tvss4 dvss4 dvss3 dvss2 dvss1rvss2 rvss1rvss3 rvss4 rvss5 tvss1 tvss2 tvss3 vss3 vss2 vss1vss5 vss4vss6 rvdd1rvdd2 tvdd 3vdd13vdd2 3vdd3 3vdd4 3vdd5 3vdd6 3vdd7 3vdd8 3vdd9 3vdd103vdd11 3vdd12 3vdd13 3vdd14 3vdd15 3vdd16 dvdd8 dvdd7 dvdd6 dvdd5 dvdd4 dvdd2dvdd3 dvdd1 1.8vdd13 1.8vdd11 1.8vdd12 1.8vdd10 1.8vdd51.8vdd7 1.8vdd6 1.8vdd31.8vdd9 1.8vdd8 vss27 vss26 vss25 vss24 vss23 vss22 vss21 vss20 vss19 vss18 vss16vss17 vss15 vss14 vss13 vss12 vss11 vss10 vss9 vss8 vss7 v3_3 v3_3 max1792 in outset gnd out in shdn rst downloaded from: http:///
serial signals with off port flags goto the 140 pin wan connectors jumpers for ethernet rser rclk rden - valid combinations: place testpoints for ethernet dataen and clk near corresponding 3 pin jumper e_rden=vcc and e_rclki=s_rchclk e_rden=s_rchblk and e_rclki=s_rclk 01/05/2005 5/6(block) 10/27(total) block name: _z11andlan_dn. parent block: \_DS33R11DK_design\ steve scully ds33zh11-r11dk01a0 1 2 j11 1 2 j10 jp01 jp02 10 9 8 7 6 5 4 3 2 1 j18 10 9 8 7 6 5 4 3 2 1 j05 rb30 rb31 tp03 tp02 8 1 5 4 y03 r14 2 1 rb44 2 1 rb19 2 1 rb50 2 1 rb49 2 1 rb47 2 1 rb51 2 1 rb54 2 1 rb14 2 1 rb46 2 1 rb45 z_rden z_tser z_rserz_tden fullds modec1 dcedtes hwmode modec0 rmiimiis afcs scanmod scanen 2.0k s_rchclk s_rclk s_tchclk s_tclk s_tclko 100.000mhz_3.3v 10k 10k z_jtclk z_jtms z_jtdiz_jtdo z_jtrst 2.0k2.0k 2.0k 2.0k 2.0k 2.0k2.0k 2.0k s_tchblk mdcmdio s_rchblk s_tser sd_clki 30 s_rser z_tclkiz_rclki 2.0k h10s page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 v3_3 v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p 6 10 8 4 1 2 3 5 7 9 conn_10p v3_3 vcc 1 osc gnd out v3_3 v3_3 v3_3 downloaded from: http:///
spare inverters all unmarked bias resistors are 10k end of ds33r11 hierarchy block 6/6(block) steve scully ds33zh11-r11dk01a0 11/27(total) 01/05/2005 block name: _z11andlan_dn. parent block: \_DS33R11DK_design\ a d g b c f h e rb53 rb69 rb58 rb73 rb52 rb83 r09 jp04 rb61 rb59 rb39 rb37 rb60 rb38 rb63 10 9 8 7 6 5 4 3 2 1 j06 rb34rb36 8 1 5 4 y01 10 9 8 7 6 5 4 3 2 1 j13 10 9 8 7 6 5 4 3 2 1 j12 1 2 cb105 rb35 2 1 rb91 r13 2 1 rb87 r10 r07 r12 c11 rb33 tpb03 rb32 tpb04 4 1 u07 12 1 10 3 11 2 tb01 9 4 7 6 8 5 tb01 8 7 6 5 4 3 2 1 j20 4 1 u06 tpb06 1 5 4 3 2 j19 tpb05 1 2 j17 1 5 4 3 2 j24 1 2 j25 s_liuc s_tsync s_bpclk s_rdata s_8xclk s_rsysclk s_tnegi s_tposi 3030 s_tser s_rsysclk s_tsync s_liuc 10k s_rnegi s_rposo s_tsysclk s_jtms s_mclk rj_pin5 s_tclk s_rclk s_mclk s_teso s_tclko s_tdata s_tnego s_tposo s_rclki s_rposi 3030 30 30 10k 10k 10k rring s_jtdo s_jtdi s_jtclk tring ttip rj_pin5 rj_pin2 rj_pin4 rj_pin1 rtip 10k 0.1uf 30 0.0 60.4 0.0 0.0 0.0 10k 10k s_jtrst 10k s_tssync rj_pin1 60.4 s_tsig inverter inverter 10k10k s_tclki 30 s_rnego s_rclko 10k 1uf 2.048mhz_3.3v rj_pin4 rj_pin2 s_rfsync s_tsysclk s_tssync s_tsig s_rsync s_rmsync s_rsigf s_rsig s_rlos s_rcl page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 nc7sz86_u conn_bnc_5p v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p v3_3 vcc 1 osc gnd out 6 10 8 4 1 2 3 5 7 9 conn_10p 6 10 8 4 1 2 3 5 7 9 conn_10p conn_bnc_5p nc7sz86_u 1:1 1:2 conn_rj48 e h f c b g d a v3_3 downloaded from: http:///
beginning of processor hierarchy block block name: _motprocrescard_dn. parent block: \_DS33R11DK_design\ printed fri sep 23 11:01:52 2005 12/27(total) steve scully 01/05/2005 1/6(block) ds33zh11-r11dk01a0 mr* gnd vcc reset* vdd4 vdd1 vdd2 d20d19 d18 d17 d16d15 d14 d13 d12 d11 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d10 d9d8 d7 d6 d5 d4 d3 d2 d1 d0 vssavssf vsssyn vss8 vss7 vss6 vss5 vss4 vss3 vss2 vss1 a0 a1 a2 a3 a4 a5 a6 a7 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 d31 a8 vrl rw vdd5vdd3 vddsyn vdd8vdd7 vdd6 vpp vddavddf vddh tea* vstby vrh oe* shs* ta* txd1 rxd2 int4 int5*int2* int3* xtal miso mosi yc0 int0* tms cs0* reset*clkout rstout* sckde* cs2*cs1* cse0 tc2 eb2*eb1* eb0* pqb3 pqb2 pqb1 int6* eb3* cse1 tdo tdi tc1 cs3* pqa1 pqa0 pqa3 pqa4 pqb0 ss* trst* tclk extal icoc22 icoc23icoc20 icoc21icoc11 icoc12 icoc13 int1* test icoc10 txd2 int7* rxd1 rb26 c02 80 124 6669 142138 63 135 133 130 67 78 94 93 68 70 120 118 104105 106 107 108 109 110 111 90 91 89 88 8482 7975 72 71 5253 54 55 56 57 58 61 125 9698 100101 143 6062 81 8385 86 128 u03 92 126 73 114140 127 76 6444 32 18 8 112 113 87 123 103 74 115141 129 77 6545 33 19 9 102 99 97 5995 3738 39 40 41 42 144 1 43 2 3 45 7 1012 15 16 17 46 20 21 2225 27 30 31 3435 36 48 51 1314 2324 26 28 29 116 117 119 47 121 122 131 132134 136 137 139 6 11 4950 u03 42 3 1 u01 4 3 2 1 sw01 rb29cb33 pqb0 pqb2 pqb3 kit_status int2 osc_mcuonce_tclk once_trst_b 1uf 17 tc2 ss ta rcon oe vrh tea rw sci1_in user_led1 sci2_out icoc10 test icoc13icoc12 icoc11 icoc21icoc20 icoc23icoc22 pqa4pqa3 pqa0 pqa1 cs3 tc1 once_tdi 2107_tdo cse1 eb3 tim_16h_8l pqb1 eb0 eb1 eb2 cse0 cs1 cs2 cpuclk_out cs0 once_tms yco mosi miso xtal int4 run_kit_usr user_led2 int3 sci2_in sci1_out 2520 2.93v 22 1312 11 10 8 9 7 65 3 21 4 1 0 .1uf 0.0 20 0 2 3 4 5 31 30 2927 19 2826 24 23 6 7 8 9 10 21 18 19 17 18 1613 12 11 1615 14 gnd pa<22..0> 2 pd<31..0> 1 22 1514 vddsyn flash_vpp once_de_b sck proc_reset_out proc_reset proc_reset 1.0k reset page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 mmc2107control rxd1 int7* txd2 icoc10 test int1* icoc13icoc12 icoc11 icoc21icoc20 icoc23icoc22 extaltclk trst* ss* pqb0pqa4 pqa3 pqa0 pqa1 cs3* tc1 tdi tdo cse1 eb3* int6* pqb1 pqb2 pqb3 eb0* eb1* eb2* tc2 cse0cs1* cs2* de* sck rstout* clkout reset* cs0* tms int0* yc0mosi misoxtal int3*int2* int5* int4 rxd2 txd1 mmc2107 port ta* shs* oe* vrh vstby tea*vddh vddf vdda vpp vdd6 vdd7 vdd8 vddsyn vdd3 vdd5 rw vrl a8 d31 a22 a21 a20a19 a18 a17 a16a15 a14 a13 a12 a11 a10 a9a7 a6 a5 a4 a3 a2 a1 a0 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vsssyn vssf vssa d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d30d29 d28 d27 d26d25 d24 d23 d22 d21d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 vdd2 vdd1 vdd4 v3_3 max811_u reset* vcc gnd mr* v3_3 downloaded from: http:///
reset and chip configuration xtal w/ pll boot internal d18 has a 10k load to gnd d18 has a 10.5k load to v3v boot ext when set for intern/extern boot reset configuration full drive master mode internal flash enable ds33zh11-r11dk01a0 steve scully 01/05/2005 2/6(block) 13/27(total) block name: _motprocrescard_dn. parent block: \_DS33R11DK_design\ io7io6 io5 io4 io3 io2 io1 io0 a8 a9 a10 a11 a12 a13 a14 a15 a16 vccgnd oe* we* n_c a0 a1 a2 a3 a4 a5 a6 a7 ce2 ce1* io7 io6io5 io4 io3 io2 io1 io0 a8 a9 a10 a11 a12 a13 a14 a15 a16 vccgnd oe* we* n_c a0 a1 a2 a3 a4 a5 a6 a7 ce2 ce1* 2 1 rb12 2 1 1 rb22 2 1 rb10 2 1 1 rb18 2 1 1 rb17 2 1 rb11 1 2 1 rb09 1 2 1 rb13 2 1 1 rb08 29 32 24 1 21 20 1918 17 15 14 13 16 30 22 2627 56 7 89 10 2 31 3 28 4 2523 11 12 u05 2 1 1 rb07 29 32 24 1 21 20 1918 17 1514 13 16 30 22 2627 56 7 89 10 2 31 3 28 4 2523 11 12 ub03 pa<17..1> pd<23..16> pd<31..24> pd<18> pd<19> pd<28> pd<22> pd<23> pd<21> pd<16> pd<17> pd<26> 16 10k 10k 10k 10k 10k 10k 10k 17 10k 10k 18 20 9 10 11 12 8 7 65 19 13 14 1615 17 4 3 2 1 24 21 25 26 27 28 29 30 31 10k 22 9 10 11 12 13 14 16 8 7 65 4 3 2 1 15 17 oe eb0cs0 cy62128v pa<17..1> cy62128v oe eb1 cs0 rcon 23 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 cy62128v ce1* ce2 a7a6 a5 a4 a3 a2 a1 a0 n_cwe* oe* gnd vcc a16a15 a14 a13 a12 a11 a10 a9a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 cy62128v ce1* ce2 a7a6 a5 a4 a3 a2 a1 a0 n_cwe* oe* gnd vcc a16a15 a14 a13 a12 a11 a10 a9a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 downloaded from: http:///
but do not populate jtag configuration align key pin oncetdi mmc2107 oncetdo pin tdi ...fpga+flash... place pads for cap 3/6(block) 01/05/2005 steve scully ds33zh11-r11dk01a0 block name: _motprocrescard_dn. parent block: \_DS33R11DK_design\ 14/27(total) r2in r2outr1in t1inforceon r1out t1out vcc forceoff* v+1 v+2 c1+ c1- c2+ c2- v- gnd t2out t2in invalid* j e d b ac fg h 1 2 1 rb23 2 1 ds04 2 1 rb21 2 1 ds03 1 2 j03 2 1 1 rb24 1 2 xb01 1 2 1 r01 2 1 rb27 1 2 1 rb28 9 8 7 6 5 4 3 2 1 j02 1 2 1 rb03 1 2 1 rb06 9 17 12 11 19 3 7 4 1 20 68 2 18 5 10 1615 14 13 ub01 2 1 rb01 2 1 1 rb25 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j04 kit_status prt1_out sci1_in sci1_out prt1_in once_trst_b once_de_b once_tms con14p 10k osc_mcu prt1_in prt1_out xtal 10k 10k 10k 10k 10k 1.0m 8.0mhz proc_reset once_tclk 2107_tdo once_tdi 1.0k flash_vpp red 330 330 green user_led1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 v3_3 conn_db9p h g f c a b de j v3_3 max3233e invalid* t2in t2out gnd v- c2-c2+ c1- c1+ v+2 v+1 forceoff* vcc t1out r1out forceon t1inr1in r2out r2in v3_3 con14p downloaded from: http:///
mem_so / run_drv install jumper to run device driver mem_si / tclkeqrclk install jumper to set tclk=rclk mem_cs / en_ints install jumper to enable interrupt service mem_sck must be at pin77 for tqfp144 block name: _motprocrescard_dn. parent block: \_DS33R11DK_design\ 01/05/2005 steve scully ds33zh11-r11dk01a0 4/6(block) 15/27(total) pr12b/di/csspi* pr11b/busy/sispi pr11a/d7/spid0 pt17b/pclkc0_0 pr15b pl9a/pclkt7_0 pr16b pr18a/vref1_3 pr16a pr15a/rdqs15 pr14b/rlm0_pllc_fb_a pr13b/rlm0_pllc_in_a pr13a/rlm0_pllt_in_a pr9b/pclkc2_0 pr9a/pclkt2_0 pr8b pr8a pr7a pr7b pr2a/vref2_2pr2b/vref1_2 pt18a pt18b pt19a/vref1_1 pt13a pt13b pt19b/vref2_1 pt20b pt21a pt20a pt21b pt22a/tdqs22 pt22b pt23apt25a pt25b pl8a pl8b pl7b pl7a pl2b/vref1_7 pl2a/vref2_7 pb24b/d5/spid2pb25b/d6/spid1 pb23b/d4/spid3 pb22b/d3/spid4 pb21b/d1/spid6 pb20b/d0/spid7 pl16a pb10apb11a pb11bpb13b pb14a/bdqs14 pb14b pb15a pb15bpb16b/vref1_5 pb16a/vref2_5pb17b/pclkc5_0 pb18a/write* pl18a/vref1_6pl18b/vref2_6 pl16b pl15a/ldqs15pl15b pl14b pl12b/llm0_pllc_fb_a pl12a/llm0_pllt_fb_a pl11b/llm0_pllc_in_a pl11a/llm0_pllt_in_a pb18b/cs1*pb21a/d2/spid5 pb22a/bdqs22 pb23a pb10b pt10b pt10a pt14a/tdqs14 pb20a/vref2_4 pb19b/cs* pb19a/vref1_4 pb17a/pclkt5_0 pt12a pt12b pl13a pl13b pl14a pt14b pr12a/dout/cso* pr14a/rlm0_pllt_fb_a pt16a/vref2_0 pt15b pt15a pt17a/pclkt0_0 pt16b/vref1_0 pl9b/pclkc7_0 rb15 ds01 rb16 111 112 113 114 115 116 118 119 120 121 122 123 124 127 129 130 131 132 133 134 135 137 138 139 140 141 142 100 101 102 103 104 105 106 107 74 75 76 77 78 79 81 82 83 85 8687 88 9 8 7 6 5 4 3 2 35 34 33 32 31 30 29 27 26 25 23 22 21 20 70 69 68 67 66 65 64 62 61 60 59 58 57 56 53 51 50 49 48 47 46 45 43 42 41 40 39 u04 fpga_zhspics wr_dut pd<31..16> 23 reset_ah cs_x1 cs_x6 cs_x2 cs_x5 cs_x3cs_x4 reset cs2 cs1 cs0 rw oe int2 int_led rd_dut 330 0 1 2 3 4 5 6 7 d_dut<7..0> 0.0 pa<16..0> 16 17 18 19 20 21 22 24 25 26 28 30 31 2927 cpuclk_out a_dut_<9..0> 0 1 2 3 45 6 7 89 0 1 2 3 45 6 7 89 10 11 1213 14 15 16 int5 userfpga2 mem_sck ale_dut 97_io fpga_zhmosi fpga_zhspisck fpga_zhmiso eb0 eb1 mem_so run_drv tclkeqrclk en_ints mem_cs mem_si page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 bank 3 lfec_t144_u bank 0 i/o port bank 6 bank 4 bank 5 bank 1 bank 2 input pll pll input pll input bank 7 input pll input pll pll input pl9b/pclkc7_0 pt16b/vref1_0 pt17a/pclkt0_0 pt15a pt15b pt16a/vref2_0 pr14a/rlm0_pllt_fb_a pr12a/dout/cso* pt14b pl14a pl13b pl13a pt12b pt12a pb17a/pclkt5_0pb19a/vref1_4 pb19b/cs* pb20a/vref2_4 pt14a/tdqs14 pt10a pt10b pb10b pb23a pb22a/bdqs22 pb21a/d2/spid5 pb18b/cs1* pl11a/llm0_pllt_in_apl11b/llm0_pllc_in_a pl12a/llm0_pllt_fb_a pl12b/llm0_pllc_fb_a pl14bpl15b pl15a/ldqs15pl16b pl18b/vref2_6 pl18a/vref1_6 pb18a/write* pb17b/pclkc5_0 pb16a/vref2_5pb16b/vref1_5 pb15b pb15a pb14b pb14a/bdqs14 pb13b pb11b pb11a pb10a pl16a pb20b/d0/spid7pb21b/d1/spid6 pb22b/d3/spid4 pb23b/d4/spid3 pb25b/d6/spid1 pb24b/d5/spid2 pl2a/vref2_7pl2b/vref1_7 pl7a pl7bpl8b pl8a pt25b pt25a pt23a pt22b pt22a/tdqs22 pt21b pt20apt21a pt20b pt19b/vref2_1 pt13b pt13a pt19a/vref1_1 pt18b pt18a pr2b/vref1_2 pr2a/vref2_2 pr7b pr7apr8a pr8b pr9a/pclkt2_0pr9b/pclkc2_0 pr13a/rlm0_pllt_in_apr13b/rlm0_pllc_in_a pr14b/rlm0_pllc_fb_a pr15a/rdqs15 pr16a pr18a/vref1_3 pr16b pl9a/pclkt7_0 pr15b pt17b/pclkc0_0 pr11a/d7/spid0 pr11b/busy/sispi pr12b/di/csspi* out in out out downloaded from: http:///
block name: _motprocrescard_dn. parent block: \_DS33R11DK_design\ 5/6(block) ds33zh11-r11dk01a0 steve scully 01/05/2005 16/27(total) 2 1 r2 2 1 r1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j07 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j08 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j09 2 1 rb40 2 1 rb41 2 1 rb42 2 1 rb43 tclkeqrclk en_ints run_drv 10k 10k 10k int3 nopop int2 a_dut_<9..0> 10k wr_dut resetcs_x2 cs_x4cs_x3 rd_dut cs_x1 int3int2 nopop 7 6 5 4 3 2 1 a_dut_<9..0>d_dut<7..0> int4 10k 10k reset_ah reset cs_x4 int4 int5 cs_x2 cs_x5 cs_x1 rd_dut wr_dut cs_x3 int2 int3 0 nopop int5 0 1 2 d_dut<7..0> 3 4 5 6 7 8 9 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 out out out v3_3 out v3_3 out 2 3 7 13 8 59 11 6 4 1012 14 1 conn_14p 2 3 7 13 8 59 11 6 4 1012 14 1 conn_14p 2 3 7 13 8 59 11 6 4 1012 14 1 conn_14p out outout in in inin io out out v3_3 downloaded from: http:///
end of processor hierarchy block 17/27(total) 6/6(block) 01/05/2005 steve scully ds33zh11-r11dk01a0 block name: _motprocrescard_dn. parent block: \_DS33R11DK_design\ vccio6b vccio7 gnd5gnd6a gnd4nc2 nc1 gnd0gnd1 gnd2/gnd1gnd3a/gnd4 gnd3b gnd6b/gnd5 gnd7/gnd0 gnd8gnd9 gnd10 done tck vccio6a vccio5b vcc1vcc2 tmscfg0 cfg2cfg1 cclk vccio0a program* init* vccio0bvccio1a vccio1b vccio2 vccio5a vccio4b vccio3a tdo tdi vcc3vccj vccaux1 vccaux2 xres vccio3bvccio4a cs* sck so vcc hold* wp*gnd si in ic out rst* gnd shdn* 3 4 6 1 5 2 ub02 3 8 2 56 7 4 1 u02 10 9 8 7 6 5 4 3 2 1 j01 cb24cb23 cb26 cb12 cb25 cb29 rb05rb04 10 19 1 36 24 44 38 71 55 84 73 108 125 110 143 136 126 54 99 92 13 17 18 16 14 93 12 11 95 96 15 144 37 28 52 63 80 72 109 98 117 128 97 8990 91 94 u04 rb02 1 tpb01 1 tpb02 r02 i28 i26 i24 i10 i6 i5 mem_si mem_somem_sck mem_cs l_tdo l_tdi l_tdil_tdo reset mem_sck l_tms l_tck v1_2 l_tck l_tms v1_2 2.7v .1uf.1uf .1uf 10uf 10uf 10uf 10k10k 97_io 10k 10k page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max1963 shdn*gnd rst* out ic in v3_3 at25160a_u si gnd wp* hold* vcc so sckcs* conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo v3_3 v3_3 control lfec_t144_u all low for spi3 mode needs 10k,1% resistor place close to pin vccio4a vccio3b xres vccaux2 vccaux1 vccj vcc3 tdi tdo vccio3avccio4b vccio5a vccio2 vccio1b vccio1a vccio0b init* program* vccio0a cclk cfg1 cfg2cfg0 tms vcc2 vcc1 vccio5bvccio6a tck done gnd10 gnd9 gnd8 gnd7/gnd0 gnd6b/gnd5 gnd3b gnd3a/gnd4 gnd2/gnd1 gnd1 gnd0 nc1 nc2 gnd4gnd6a gnd5 vccio7 vccio6b v3_3 downloaded from: http:///
page numbers (bottom right) are listed by both the page number in the block, and by the page number within the entire design cross reference indicators are referenceing a given net to other pages in the design (page number given is according to entire design, not the current block) ds33zh11 design kit mii ethernet hierarchy block t1e1 liu hierarchy block ds33zh11 hierarchy block t3e3 liu hierarchy block buffer for delay notes: all hierarchy block names end in _dn. pins on hierarchy blocks do not have pin numbers (but pins on symbols do). signals inside a hierarchy block are local to that block - the signal temp in block_a_dn is different than temp in block_b_dn. pages 20-22 pages 26-27 pages 24-25 page 23 printed fri sep 23 11:01:54 2005 1/2(block) 18/27(total) ds33zh11-r11dk01a0 01/05/2005 steve scully block name: _ds33zh11dk_design. parent block: \_ztopdn_\ zmiso rxd2rxdv tx_en txd3 txd2 txd1 txd0 rx_err rx_crs rx_clk rxd3 rxd1 rxd0 tx_clk fpga_spics zspisck zmosi ref_clko rst_zchip tser tclkirser rclki rclk rpos tpos tclk rst tpos tclki rposrclk txd0 mii_clk mdc mdio txd1txd2 txd3 tx_clk rxdv col_det rx_crsrx_err rx_clk led_dplx_add0 led_col_add1 led_gdlink_add2 led_rx_add4 led_tx_add3 rxd0rxd3 rxd2 rxd1 tx_en reset r21 rb101 rb129 rb138 rb132 4 1 ub06 2 3 1 jp06 2 3 1 jp07 2 3 1 jp08 2 3 1 jp05 2 3 1 jp11 8 1 5 4 yb04 te3_rpos te1_tpos te1_rclk zh_rxd1 zh_rxd2zh_rxd3 zh_rx_crs zh_rxdv zh_rclki zh_rser zh_tclki rst_zchip ref_clko zmosi zspisck fpga_spics zh_tx_clk zh_rxd0zh_rx_clk zh_rx_err zh_txd0 zh_txd1 zh_txd2zh_txd3 zh_tx_en zmiso zh_tser phy_clk ref_clko jmp_3 te3_tpos te3_rclk te3_tclk 30 v3_3 gnd te1_tclk led_dplx_a0 led_col_a1 led_gdlink_a2led_rx_a4 led_tx_a3 25.000mhz_3.3v rst_prf te1_rpos rst_prf buffer 30 30 30 30 1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in vcc 1 osc gnd out out in in nc7sz86_u v3_3 _mii_wan_dn reset tx_en rxd1rxd2 rxd3 rxd0 led_tx_add3led_rx_add4 led_gdlink_add2 led_col_add1 led_dplx_add0 rx_clkrx_err rx_crs col_det rxdv tx_clk txd3 txd2 txd1 mdio mdc mii_clk txd0 _te1liu_wan_dn rclk rpos tclki tpos rst _te3liu_wan_dn tclk tpos rposrclk v3_3 _zh11_dn rclki rser tclki tser rst_zchip ref_clko zmosi zspisck fpga_spics tx_clk rxd0rxd1 rxd3 rx_clkrx_crs rx_err txd0txd1 txd2 txd3 tx_en rxdv rxd2 zmiso downloaded from: http:///
ds33zh11 mii clk is gated by reset 160 us before reset deactivates mii phy requires mii clk to be stable for printed fri sep 23 11:01:54 2005 2/2(block) 19/27(total) block name: _ds33zh11dk_design. parent block: \_ztopdn_\ ds33zh11-r11dk01a0 01/05/2005 steve scully mr* gnd vcc reset* cb158cb156 cb182 c25 2 1 cb192 2 1 c34 2 1 cb196 2 1 cb191 2 1 cb152 2 1 cb176 2 1 cb186 c27 cb166cb173 cb174 cb183 c35 cb172 c33 cb164cb167 cb165 4 sw02 42 3 1 u15 rb178 cb194 2 1 ds19 rb168 2 1 ds20 rb169 rb174 2 1 ds21 rb173 rb176 rb175 2 1 ds18 rb165 rb164 2 1 ds16 rb157 rb158 4.7uf4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 4.7uf 1 470uf 1 0.1uf 1 0.1uf 1 0.1uf 1 0.1uf 1 0.1uf 1 0.1uf 4.7uf 1 10uf 1 10uf 1 10uf10uf 1 10uf 1 10uf 1 i35 i34 i20 i18 i15 i11 i8 rst_zchip rst_prf led_tx_a3 led_rx_a4 led_gdlink_a2 led_col_a1 led_dplx_a0 max811seus-t 2.93v sot143 2.0k 0.1uf 1 red 5.1k 1 1 amber 330 1 1 330 1 green 5.1k 1 1 330 5.1k 1 amber 1 330 1 5.1k 1 1 amber 1 330 5.1k 1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max811_u reset* vcc gnd mr* v3_3 v3_3 downloaded from: http:///
series termination mii tx pins usualy have zh11 package allows for close placement, resistors omitted this page are 30 ohm unmarked resistors on begining of ds33zh11 hierarchy block 01/05/2005 1/3(block) 20/27(total) steve scully ds33zh11-r11dk01a0 block name: _zh11_dn. parent block: \_ds33zh11dk_design\ sda<0> 6vdd3.3 2vdd3.3 1vdd3.3 0vdd3.3 tser sda<1> ref_clko rx_crs/crs_dv rx_err rx_clk rx_dv rxd<3> tx_clk tx_en d<1>/miso d<0>/mosid<2>/spick spi_cs* hwmode sdata<27> sdata<25> sdata<24> sdata<23> sdata<18>sdata<19> sdata<26> sdata<22> sdata<21> sdata<20> sdata<17> sdata<16> sdata<14>sdata<15> sdata<6> sdata<5>sdata<7> sdata<8> sdata<9> sdata<10>sdata<12> sdata<11>sdata<13> sdata<2>sdata<3> sdata<4> sdata<1> sdata<0> txd<3> txd<2> txd<1> txd<0> 2vdd1.8 0vdd1.8 1vdd1.8 (future a1) 5vdd3.3 3vdd3.3 tclki rclki rxd<2> rxd<1> rxd<0> 4vdd1.8 3vdd1.8 rser sda<3>sda<4> sda<6> sda<5>sda<7> sda<8> sda<9> sda<10> sda<11> sdmask<0> sdmask<1> sdmask<2> sdcs* sdmask<3> sdclko sysclkisras* scas* swe* sba<1>sda<2> modec<1>sdata<28> sdata<29> sdata<30> sdata<31> vss5 vss4 vss3 vss2 vss1 (future a2) vss0 (future a0) rst* 4vdd3.3 sba<0> rb133 e7 e6 e5 e4 b4 a5 a9 b8 b7 a8b6 a6 a2 b1 k10 g3 k3 b5 c5 j6 e3 f3 h3 j3 c6g6 g8 g9 c7 h9 h8 j9 k9 h7 j8 k7 k8 j7 g7 k6 e1 d2 d1 g1 f1 c2 e2 d3 c3 j2 k2 k1 g2 j1 f2 h1 k4 h5 f5 f8 g4 g5 h4 c4 f9 h6 k5 j5f4 j4 f7 c10 c9 d10 d9b9 a10 c8 b10 c1 b3 g10 b2 a4 a3 e10 e9 e8 h10 d8 d7 a1 d6 j10 d5 h2 d4 f10 a7f6 u11 tser sd_ba0 rst_zchip fut_a0 fut_a2 modec1 sd_ba1 sd_we sd_cas sd_ras sd_clki sd_clko sd_dqm3 sd_cs sd_dqm2 sd_dqm1 sd_dqm0 rser rxd0 rxd1 rxd2 rclki tclki fut_a1 txd0 txd1 txd2 txd3 hwmode zspics zspisck zmosi zmiso tx_en tx_clk rxd3 rxdv rx_clk rx_err rx_crs ref_clko sd_dq<31..0> 26 v1_8lvreg 9 sd_dq<31..0> 21 20 19 18 11 8 7 56 4 3 0 25 24 23 22 17 16 15 14 12 11 9 10 8 7 6 4 0 31 30 2928 27 jmp_3 10 5 3 1 2 1 2 sd_a<11..0> 13 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 in in in inin in in in in in in out outout out out v3_3 inin in out ds33zh11_u1 sba<0> 4vdd3.3 rst* vss0 (future a0) vss1 (future a2) vss2vss3 vss4 vss5 sdata<31> sdata<30> sdata<29> sdata<28> modec<1> sda<2> sba<1>swe* scas* sras* sysclki sdclko sdmask<3>sdcs* sdmask<2> sdmask<1> sdmask<0> sda<11> sda<10> sda<9> sda<8> sda<7> sda<5>sda<6> sda<4> sda<3> rser 3vdd1.8 4vdd1.8 rxd<0>rxd<1> rxd<2> rclkitclki 3vdd3.3 (future a1) 5vdd3.3 1vdd1.8 0vdd1.82vdd1.8 txd<0>txd<1> txd<2> txd<3> sdata<0>sdata<1> sdata<4> sdata<3> sdata<2> sdata<13> sdata<11>sdata<12> sdata<10> sdata<9> sdata<8> sdata<7> sdata<5>sdata<6> sdata<15> sdata<14>sdata<16> sdata<17> sdata<20> sdata<21> sdata<22> sdata<26> sdata<19> sdata<18>sdata<23> sdata<24> sdata<25> sdata<27> hwmode spi_cs* d<2>/spick d<0>/mosid<1>/miso tx_en tx_clk rxd<3> rx_dv rx_clkrx_err rx_crs/crs_dv ref_clko sda<1> tser 0vdd3.3 1vdd3.3 2vdd3.36vdd3.3 sda<0> downloaded from: http:///
config switches for z11 low low ds33zh11-r11dk01a0 21/27(total) steve scully 01/05/2005 2/3(block) block name: _zh11_dn. parent block: \_ds33zh11dk_design\ cs* sck so vcc hold* wp*gnd si rstshdn in outgnd set out in rb102 8 1 5 4 yb03 rb104 rb116 1 2 j27 rb98 1 2 j26 rb97 r15 2 3 1 jpb01 cb161 cb157cb193 cb155 cb159 cb160 cb154 1 2 cb153 2 1 cb197 2 1 cb195 2 1 c30 5 4 8 7 3 2 6 1 ub07 3 8 2 56 7 4 1 y04 rb100 rb99 fut_a1 jmp_3 zspics fpga_spics modec1 jmp_2 .1uf 4.7uf v1_8lvreg 4.7uf 4.7uf 2.7v 10uf10uf 1 1 1 1uf 1 1uf 1 1uf 2 1uf 10k 4.7uf zmiso 10k 1 30 2.0k jmp_2 2.0k 2.0k 2.0k 100.000mhz_3.3v 2.0k sd_clki hwmode fut_a0 fut_a2 zspisck zmosi page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 vcc 1 osc gnd out v3_3 v3_3 v3_3 out in in in v3_3 max1792 in outset gnd out in shdn rst at25160a_u si gnd wp* hold* vcc so sckcs* v3_3 downloaded from: http:///
be non- swapable address pins appear that they should from z11 sysclko mt48lc4m32b2 - 1 meg x 32 x 4 banks synchronous dram block name: _zh11_dn. parent block: \_ds33zh11dk_design\ ds33zh11-r11dk01a0 steve scully 3/3(block) 01/05/2005 22/27(total) vdd4vdd3 vddq6vddq1 clkcs* cke cas* we* dqm<0> ras* dqm<1>dqm<2> dqm<3> ba<0>ba<1> a<0>a<1> a<3> a<2>a<4> a<6> a<5>a<8> a<7>a<9> a<10>a<11> dq<5>dq<6> dq<7> dq<8> dq<9> dq<10> dq<11> dq<12> dq<14> dq<13>dq<15> dq<16> dq<17> dq<18> dq<20> dq<19>dq<21> dq<23> dq<22>dq<25> dq<24>dq<26> dq<27> dq<28> dq<29> vddq5vddq4 dq<4> vdd2vdd1 dq<2>dq<3> dq<1>dq<0> dq<30>dq<31> vssq8 vssq6 vssq7vssq5 vssq3 vssq4vssq1 vssq2 vss3 vss4vss1 vss2 vddq7 vddq8vddq3 vddq2 17 84 78 5246 3832 12 6 86 72 5844 81 75 5549 41 35 9 3 4329 15 1 19 59 28 71 16 56 54 53 51 50 48 47 45 42 40 39 37 36 34 33 31 85 83 82 80 79 77 76 74 13 11 10 8 7 5 42 20 6867 18 23 22 21 24 66 65 64 63 62 61 60 27 26 25 ub05 sd_ba1 sd_ba0 sd_cssd_we sd_cas sd_ras sd_dqm0 sd_dqm1 sd_dqm2 sd_clko sd_dqm3 sd_dq<31..0> sd_a<11..0> 8 7 6 5 4 29 28 27 26 25 24 23 22 3 21 20 19 18 17 16 15 14 13 2 12 11 10 9 8 6 7 5 4 3 1 2 30 31 1 0 11 10 9 0 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 mt48lc4m32b2_tsop_u vddq2 vddq3 vddq8vddq7 vss2vss1 vss4vss3 vssq2 vssq1 vssq4vssq3 vssq5 vssq7vssq6 vssq8 dq<31> dq<30> dq<0> dq<1> dq<3> dq<2> vdd1 vdd2 dq<4> vddq4 vddq5 dq<29> dq<28> dq<27> dq<26> dq<24>dq<25> dq<22>dq<23> dq<21> dq<19>dq<20> dq<18> dq<17> dq<16> dq<15> dq<13>dq<14> dq<12> dq<11> dq<10> dq<9> dq<8> dq<7> dq<6> dq<5> a<11> a<10> a<9> a<7>a<8> a<5>a<6> a<4> a<2>a<3> a<1> a<0> ba<1> ba<0> dqm<3> dqm<2> dqm<1> ras* dqm<0> we* cas* ckecs* clk vddq1 vddq6 vdd3 vdd4 v3_3 downloaded from: http:///
spare (socketed) oscillator use 34.368 mhz for e3 use 44.736 mhz for t3 begining and end of t3e3 liu hierarchy block network interface txtip rxtip rxring transmit redred grn receive txring note: center tap of t02 was not pulled to v3_3 in ds33rzh11dk01a0 revision. pin t02.2 is pulled to v3_3 with a wire in the ds33rzh11dk01a0 revision printed thu sep 22 16:21:49 2005 ds33zh11-r11dk01a0 steve scully 01/05/2005 block name: _te3liu_wan_dn. parent block: \_ds33zh11dk_design\ 23/27(total) 1/1(block) 75 ohm ra 6 cb181 .1uf 330 r22 330 ohm (1%) 2 75 ohm ra j39 prbs los dm green 330 red red 330 330 zcse tts tess tds1 tds0 rmon lbks lbo ice efe 1.0k 1.0k 1.0k 1.0k 1.0k 1.0k 1.0k 1.0k 1.0k 1.0k rx_plus rx_minus tx_minus pe-65968 .1uf 330 ohm (1%) 330 pe-65968 rclk 44.736mhz_3.3v jmp_3 34.368mhz_3.3v zcse rpos rclk tpos 10k rx_plusrx_minus rmon tx_plus mclk lbolos dm prbs tts ice lbks efe tds1 tds0 tclk tx_minus tess mclk tclk u13 8 43 10 40 13 39 2629 33 28 34 35 4244 18 2 46 15 17 16 22 9 11 5 6 20 21 37 38 1 3 4 7 1214 19 2324 25 30 31 3236 41 4547 48 27 r20 j38 3 4 5 1 2 3 45 1 t02 1 2 3 4 t03 1 2 3 46 y05 4 5 1 8 yb01 4 5 1 8 rb150 cb185 jp09 1 3 2 j28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rb127rb126 rb124 rb123 rb122 rb121 rb120 rb125 rb119 rb118 rb146 rb142rb135 ds14 1 2 ds13 1 2 ds12 1 2 tx_plus page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1:2 conn_bnc_5p conn_bnc_5p v3_3 v3_3 conn_20p 15 9 5 6 3 2 1 1618 20 8 10 7 19 17 4 12 11 1413 v3_3 vcc 1 osc gnd out vcc 1 osc gnd out v3_3 v3_3 out out in out 1:2 tx- tdso tdsi/ofsel efe ice rmontess tts* lbks* zcse* rclk rpos/rnrz rneg vss<10>vss<11> vss<12> vss<13> vss<14> vss<15> vss<16> vss<17> vss<9> vss<8> vss<5> vss<4> vss<3> vss<2> vss<0> vss<1>vss<6> vss<7> prbs dm* los* lbo vdd<0> mclk vdd<5>vdd<4> vdd<3> rx- rx+ tclktneg ds3150t tx+ tpos/tnrz vdd<2>vdd<1> downloaded from: http:///
ds21348 liu, transformers and connectors begining of t1e1 liu hierarchy block / block name: _te1liu_wan_dn. parent block: \_ds33zh11dk_design\ 01/05/2005 1/2(block) 24/27(total) steve scully ds33zh11-r11dk01a0 a d g b c f h e cb177 8 7 6 5 4 3 2 1 jb03 2 1 rb177 2 1 rb149 2 1 rb148 2 1 r18 2 1 r19 1 2 3 4 1615 14 t01 1 2 j41 2 1 r17 2 1 r16 2 1 cb180 5 6 7 8 11 10 9 t01 1 2 j40 rring tring rtip ttip 0.0 0.0 1uf 51.1 61.9 61.9 0.0 0.0 1 11 1 1 1 1 1 0603yc104mat .1uf 0l_smt0603_20pct page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 conn_bnc_5pin 1:0.8 1:1 conn_bnc_5pin conn_rj48 e h f c b g d a 1:0.8 1:1 downloaded from: http:///
configured for hw mode unmarked bias resistors are 1.0k ohm use 1.544mhz for t1 use 2.048mhz for e1 l1, l2, pbeo, bpclk = nc hardware end of t1e1 liu hierarchy block spare (socketed) oscillator 25/27(total) 2/2(block) 01/05/2005 steve scully ds33zh11-r11dk01a0 block name: _te1liu_wan_dn. parent block: \_ds33zh11dk_design\ a4_lo pbeo rcl_lotc vsm hrst* rringrpos rneg a0_hbe tclk tneg tpos tring ttip int* ad1_mm0 ad0_mm1ad2_loop1 ad3_loop0 ad4_tx1 rclk rtip a1_jas a2_jamux ad5_tx0ad6_tpd ad7_ces test vss vss1 mclk pbts_rt0 ale_sclke bpclk a3_dja bis0 bis1 vdd vdd1 wr* rd* cs* l2 l1 10 9 8 7 6 5 4 3 2 1 j36 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j29 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j31 8 1 5 4 yb02 2 3 1 jp10 8 1 5 4 yb05 rb163rb166 rb170 rb105 rb106rb107 rb109 rb111 rb108rb110 rb112 rb113 rb143rb140 rb136 rb134 rb131 rb130 rb128 rb117 rb115 rb114 rb103 rb139rb141 2 1 rb156 2 1 ds15 3 35 22 20 36 21 34 37 41 42 26 43 2728 3839 2 40 2544 24 30 5 6 23 29 1 31 33 32 4 12 13 14 15 16 17 18 19 7 8 9 10 11 u12 2.048mhz_3.3v 1.0k bis1 1.0k bis0 1.0k l1 1.0k l2 1.0k rt1 1.0k1.0k 1.0k 1.0k 1.0k 1.0k 1.0k mm1 1.0k mm0 1.0k loop1 1.0k loop0 1.0k tx1 1.0k tx0 1.0k tpd 1.0k ces 1.0k test 1.0k pbts 1.544mhz_3.3v red tclki rtip lo rst wr_nrz vsm mclk rclk ttiptpos mm0 cs_eglrd_ets tx0 1 330 rt1 ale rlos_liu tring rneg l2 jas tpd dja ces rring rpos bis1 1 pbts loop1 rclk mclk l1 hbe jamux clk1544 1.0k1.0k 1.0k 1.0k ale cs_eglwr_nrz rd_ets vsm hbe jas lo dja jamux tx1 loop0 bis0 test mm1 jmp_3 mclk page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 v3_3 out in v3_3 6 10 8 4 1 2 3 5 7 9 conn_10pconn_20p 15 9 5 6 3 2 1 1618 20 8 10 7 19 17 4 12 11 1413 conn_20p 15 9 5 6 3 2 1 1618 20 8 10 7 19 17 4 12 11 1413 vcc 1 osc gnd out v3_3 out out vcc 1 osc gnd out in ds21348 l1 l2 cs*rd* wr* vdd1 vdd bis1 bis0 a3_dja bpclk ale_sclke pbts_rt0 mclk vss1 vss test ad7_ces ad6_tpd ad5_tx0 a2_jamux a1_jas rtiprclk ad4_tx1 ad3_loop0 ad2_loop1 ad0_mm1ad1_mm0 int* ttiptring tpos tneg tclk a0_hbe rneg rpos rring hrst* vsm rcl_lotc pbeo a4_lo downloaded from: http:///
beginning of mii ethernet hierarchy block placement note: leds need to be attached outside of module due to be placed close to pin c1 and rbias must componets for testpoints (shown above) must be placed the same for each port to 0.2 between connectors. allow use of a different phy card if desired. placement should allow on z44 card all 4 ports must be placed with equal spacing and a common center line strap adapting option of dp83847 analog supply caps to be placed close to pin 14 of phy 1 jmp_2jmp_2 jmp_2 5.1k led_gdlink_add2 led_speed<1> 0.1uf 10uf 10uf 10uf 0.1uf 0.1uf txd2 txd3txd0 txd1 30 mdio mdc 5.1k rxdv rxd0 rx_errrx_clk rxd1rxd2 rxd3 rx_crs col_det tx_clk tx_en 5.1k 0.1uf 0.1uf c1pin 1 330 an_v3_3 rbias led_rx_add4 led_col_add1 mii_clk 0.1uf reset 10.0k 10uf led_tx_add3 led_dplx_add0 an_v3_3 amber an_en an1an0 10uf 0.1uf 0.1uf 0.1uf reserved14reserved15 led_tx/phyad3 led_gdlnk/phyad2 reserved3 mdc mdio led_dplx/phyad0 led_col/phyad1 led_rx/phyad4 led_speed an_en an_1an_0 x1 x2 c1 reset* rbias reserved1 reserved2 vdd3 vdd2 vdd1 vdd/ana_vdd vdd/io_vdd2 vdd/io_vdd1 reserved9 reserved8 reserved7 reserved6 reserved5 reserved4 reserved11 reserved10 gnd5 gnd4 gnd3 gnd2 gnd1 reserved18 reserved17 reserved16 reserved13 reserved12 1/2(block) 01/05/2005 steve scully ds33zh11-r11dk01a0 printed fri jun 30 02:47:52 2006 26/27(total) block name: _mii_wan_dn. parent block: \_ds33zh11dk_design\ rb147 rb160 rb145 rb162 50 51 5455 61 5860 62 64 65 44 47 58 9 1213 34 2856 14 57 5963 2 1 3 46 4248 49 15 16 17 18 19 22 23 24 25 4 21 20 53 52 u14 rb167 2 1 cb178 2 1 cb179 6 5 4 9 7 3 10 8 1 2 j30 6 5 4 9 7 3 10 8 1 2 j33 rb161 1 2 ds17 tpb10 tpb11 2 1 j34 2 1 j32 2 1 j35 2 1 cb169 2 1 c29 2 1 c26 2 1 cb187 2 1 cb184 2 1 cb188 cb163 c31 2 1 cb171 2 1 c32 2 1 cb170 2 1 cb168 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 io v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p v3_3 out out out out out out out out out 6 10 8 4 1 2 3 5 7 9 conn_10p in out in in in v3_3 in in in control dp83847_u1 reserved14reserved15 led_tx/phyad3 led_gdlnk/phyad2 reserved3 mdc mdio led_dplx/phyad0 led_col/phyad1 led_rx/phyad4 led_speed an_en an_1an_0 x1 x2 c1 reset* rbias reserved1 reserved2 vdd3 vdd2 vdd1 vdd/ana_vdd vdd/io_vdd2 vdd/io_vdd1 reserved9 reserved8 reserved7 reserved6 reserved5 reserved4 reserved11 reserved10 gnd5 gnd4 gnd3 gnd2 gnd1 reserved18 reserved17 reserved16 reserved13 reserved12 v3_3 io io io io io in downloaded from: http:///
resistors for td+-/rd+- should be placed close to xfrm should be placed close to phy end of mii ethernet hierarchy block caps for xfrm center tap rx_clktx_clk 3030 rx_err tx_entxd0 txd1 txd2 3030 txd3 sym_1 rd_p td_p rd_n .1uf 54.954.9 49.9 30 rxd1rxd2 rxd3 30 30 rx_crs col_det rd_p rd_n td_n td_p rxdv .1uf .1uf td_n 49.9 rxd0 30 rx_er/pause_en* rx_dv txd<1> txd<0> tx_en tx_er tx_clk crs/led_cfg* td+td- rxd<2> rxd<0>rxd<1> rx_clk txd<3>rxd<3> rd- rd+ txd<2> col p5 p1 sh2 p4p3 p6 p8 p2 sh1 01/05/2005 ds33zh11-r11dk01a0 steve scully 2/2(block) 27/27(total) block name: _mii_wan_dn. parent block: \_ds33zh11dk_design\ rb159 rb152 rb153 9 28 6 3 4 10 1 5 j37 cb190 cb162 rb171 cb189 rb172 r24r23 rb137 rb144rb154 rb155 43 40 7 6 26 41 32 29 30 27 11 10 45 36 35 37 3839 31 33 u14 rb151 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 port dp83847_u1 rx_er/pause_en* rx_dv txd<1> txd<0> tx_en tx_er tx_clk crs/led_cfg* td+td- rxd<2> rxd<0>rxd<1> rx_clk txd<3>rxd<3> rd- rd+ txd<2> col v3_3 conn_hfj11_2450_u j1 j2j3 j6 j4,5j7,8 p5 p1 sh2 p4p3 p6 p8 p2 sh1 downloaded from: http:///

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